Datasheet Microchip PL611-30-001 — Datenblatt

PL611-30
Programmable Clock
FEATURES PIN CONFIGURATION XIN, FIN 1 GND 2 CLK0
K
CLK1 3
4 PL611-30 п‚ Advanced programmable PLL design
п‚ Very low Jitter and Phase Noise (< 40ps Pk -Pk typ.)
п‚ Supports complementary LVCMOS outputs to drive
LVPECL and LVDS inputs.
п‚ Output Frequencies:
o < 400MHz at 3.3V
o < 350MHz at 2.5V
п‚ Input Frequencies:
o Fundamental Crystal: 10MHz -30MHz
o 3RD overtone Crystal: Up to 75MHz
o Reference Input: Up to 200MHz
п‚ Accepts 2.25V) VDD Sensitivity Frequency vs. V DD+/-10% -2 Input (F IN ) Signal Amplitude
Output Frequency
OE Enable Time Output Rise Time
Output Fall Time Internally AC coupled MHz 10 ns 10 ms 2 ppm 15pF Load, 10/90%V DD , Standard Drive 2.5 3.5 15pF Load, 10/90%V DD , High Drive 1.0 1.5 15pF Load, 90/10%V DD , Standard Drive 2.5 3.5 15pF Load, 90/10%V DD , High Drive 1.0 1.5 50 55 % 500 ps Duty Cycle At V DD/2 Max. output skew between
same frequency clocks Equal loading (15pF). Equal frequency &
drive strength Period Jitter, peak-to-peak*
(10,000 samples measured) With capacitive decoupling between V DD …