Datasheet Intersil HCS32MS — Datenblatt

DATASHEET
HCS32MS FN3057
Rev 1.00
April 11, 2007 Radiation Hardened Quad 2-Input OR Gate
The Intersil HCS32MS is a Radiation Hardened Quad 2-Input
OR Gate. A low on both inputs forces the output to a low state.
The HCS32MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of the
radiation hardened, high-speed, CMOS/SOS Logic Family. Total Dose 200k RAD (Si) SEP Effective LET No Upsets: >100 MEV-cm2/mg Latch-Up Free Under Any Conditions Ordering Information
PART
MARKING 3 Micron Radiation Hardened SOS CMOS Single Event Upset (SEU) Immunity < 2 x 10-9
Errors/Bit-Day (Typ) The HCS32MS is supplied in a 14 Ld Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix). PART
NUMBER Features TEMP.
RANGE (В°C) PACKAGE HCS32DMSR Q 5962R95 -55В°C to +125В°C 14 Ld SBDIP
78101VCC PKG.
DWG. #
D14.3 HCS32KMSR Q 5962R95 -55В°C to +125В°C 14 Ld Ceramic K14.A
78101VXC
Flatpack Military Temperature Range: -55В°C to +125В°C Significant Power Reduction Compared to LSTTL ICs DC Operating Voltage Range: 4.5V to 5.5V Input Logic Levels VIL = 30% of VCC Max HCS32D/
Sample +25В°C 14 Ld SBDIP HCS32K/
Sample +25В°C 14 Ld Ceramic
Flatpack Input Current Levels Ii п‚Ј 5ВµA @ VOL, VOH HCS32HMSR +25В°C Die Functional Diagram Intersil Pb-free hermetic packaged products employ SnAgCu or Au …