Hermetic Packages for Integrated Circuits
Ceramic Leadless Chip Carrier Packages (CLCC)
J20.A MIL-STD-1835 CQCC1-N20 (C-2)
20 PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE 0.010 S E H S
D INCHES D3 j x 45o E3 B E h x 45o
0.010 S E F S
A PLANE 2
PLANE 1 -E-MIN MAX MIN MAX NOTES A 0.060 0.100 1.52 2.54 6, 7 A1 0.050 0.088 1.27 2.23 -B --B1 0.022 0.028 0.56 0.71 2, 4 B2 0.022 0.15 0.56 -0.342 0.358 8.69 9.09 -D1 0.200 BSC 5.08 BSC D2 0.100 BSC 2.54 BSC D3 -0.358 -E 0.342 0.358 8.69 L -H-L3 0.200 BSC E2 0.100 BSC E3 -e j e -0.006 h B1 1.83 REF D e1 0.007 M E F S H S 0.072 REF B3 E1 A1 MILLIMETERS SYMBOL 0.358 0.050 BSC
0.015 -0.040 REF
0.020 REF -9.09 2 9.09 -5.08 BSC -2.54 BSC
-9.09
1.27 BSC 0.38 2
-2 1.02 REF 5 0.51 REF 5 L 0.045 0.055 1.14 1.40 -L1 0.045 0.055 1.14 1.40 -L2 0.075 0.095 1.91 2.41 -L3 0.003 0.015 0.08 0.38 -ND 5 5 NE 5 5 3
3 N 20 20 3
Rev. 0 5/18/94 -F-NOTES:
B3 E1 E2 L2
B2 L1
D2 e1
D1 1. Metallized castellations shall be connected to plane 1 terminals
and extend toward plane 2 across at least two layers of ceramic
or completely across all of the ceramic layers to make electrical
connection with the optional plane 2 terminals.
2. Unless otherwise specified, a minimum clearance of 0.015 inch …
