Datasheet Intersil ISL1218 — Datenblatt

HerstellerIntersil
SerieISL1218

Low Power RTC mit batteriegepuffertem SRAM

Datenblätter

ISL1218 Datasheet
PDF, 899 Kb, Revision: 2017-12-01
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Preise

Verpackung

ISL1218IBZISL1218IBZ-TISL1218IUZISL1218IUZ-T
N1234
Package8 Ld SOIC8 Ld SOIC T+R8 Ld MSOP8 Ld MSOP T+R

Parameter

Parameters / ModelsISL1218IBZISL1218IBZ-TISL1218IUZISL1218IUZ-T
Alarms1111
Battery BackupYesYesYesYes
Battery SealYesYesYesYes
CPU Supervisory Function PORNoNoNoNo
CPU Supervisory Function Watchdog TimerNoNoNoNo
Crystal Frequency TrimmingYesYesYesYes
DescriptionLow Power RTC with Battery Backed SRAMLow Power RTC with Battery Backed SRAMLow Power RTC with Battery Backed SRAMLow Power RTC with Battery Backed SRAM
FOUTIRQ_bar/FOUTIRQ_bar/FOUTIRQ_bar/FOUTIRQ_bar/FOUT
Freq. Out PinYesYesYesYes
IBAT400 nA400 nA400 nA400 nA
IRQ PinYesYesYesYes
IRQ_BarIRQ_bar/FOUTIRQ_bar/FOUTIRQ_bar/FOUTIRQ_bar/FOUT
Memory TypeRAMRAMRAMRAM
Operating Temperature Range-40 to 85-40 to 85-40 to 85-40 to 85
Oscillator Compensation (ppm)-94 to +140-94 to +140-94 to +140-94 to +140
Peak Temp260°C260°C260°C260°C
Qualification LevelStandardStandardStandardStandard
RESET_barNoNoNoNo
ResetNoNoNoNo
SRAM8 Bytes8 Bytes8 Bytes8 Bytes
Selectable Frequency Output15151515
Tamper DetectNoNoNoNo
Time Keeping Current1.2 μA1.2 μA1.2 μA1.2 μA
TimerNoNoNoNo
VBAT (max)5.5 V5.5 V5.5 V5.5 V
VBAT (min)1.8 V1.8 V1.8 V1.8 V
VCC (max)5.5 V5.5 V5.5 V5.5 V
VCC (min)2.7 V2.7 V2.7 V2.7 V
VTRIP for PORYesYesYesYes
interfaceI2CI2CI2CI2C

Öko-Plan

ISL1218IBZISL1218IBZ-TISL1218IUZISL1218IUZ-T
RoHSCompliantCompliantCompliantCompliant

Modellreihe

Herstellerklassifikation

  • Timing & Digital ICs > Real Time Clocks > Real Time Clocks