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  Bus Buffers Simplify Design of Large, Noisy I2C Systems &mdash LT Journal
  PDF, 3.0 Mb, Datei veröffentlicht: Jan 17, 2013
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  design features Bus Buffers Simplify Design of Large, Noisy I2C Systems
  Rajesh Venugopal The original I2C specification limited the
  maximum bus operating frequency to
  100k Hz; it is now 400k Hz . As systems grew
  larger, bus buffers were introduced to
  buffer bus capacitance and solve several other common I2C issues. Early bus buffers degraded certain I2C specifications
  in a manner that can be unacceptable
  in large noisy systems. The LTC4313 and
  LTC4315 family of bus buffers offers the
  benefits of traditional bus buffers while
  maintaining compliance to all I2C voltage DRIVER HIGH
  0.9 VCC
  0.7 VCC
  VOLTAGE The I2C bus and its derivatives—such as SMBus, PMBus,
  the DDC bus of HDMI and IPMB bus of ATCA—are used in
  a variety of large systems to transfer vital system information.
  These bus specifications have gained wide acceptance
  due to ease of use. The I2C bus is a digital serial 2-wire
  bus consisting of a single clock (SCL) and single data
  (SDA) line. The I2C protocol employs open drain pull-downs
  to drive the bus low, and resistors or current sources to
  pull the bus high. The maximum allowed pull-up current
  and bus capacitance are 4mA and 400pF, respectively. LOGIC HIGH …

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• Interface > I2C and SMBus Bus Buffers and Accelerators

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LTC4315CMSPBF, LTC4315CMS PBF