Datasheet Microchip TN5325 — Datenblatt
| Hersteller | Microchip |
| Serie | TN5325 |
Dieser Enhancement-Mode-Transistor mit niedriger Schwelle (normalerweise ausgeschaltet) verwendet eine vertikale DMOS-Struktur und ein bewährtes Silizium-Gate-Herstellungsverfahren
Datenblätter
TN5325 N-Channel Enhancement-Mode Vertical DMOS FET Data Sheet
PDF, 865 Kb, Revision: 04-05-2017
Auszug aus dem Dokument
Preise
Status
| TN5325K1-G | TN5325N3-G | TN5325N3-G-P002 | TN5325N8-G | |
|---|---|---|---|---|
| Lifecycle Status | Production (Appropriate for new designs but newer alternatives may exist) | Production (Appropriate for new designs but newer alternatives may exist) | Production (Appropriate for new designs but newer alternatives may exist) | Production (Appropriate for new designs but newer alternatives may exist) |
Verpackung
| TN5325K1-G | TN5325N3-G | TN5325N3-G-P002 | TN5325N8-G | |
|---|---|---|---|---|
| N | 1 | 2 | 3 | 4 |
| Package | SOT-23 | TO-92 | TO-92 | SOT-89 |
| Pins | 3 | 3 | 3 | 3 |
Parameter
| Parameters / Models | TN5325K1-G | TN5325N3-G | TN5325N3-G-P002 | TN5325N8-G |
|---|---|---|---|---|
| BVdss min, V | 250 | 250 | 250 | 250 |
| CISSmax, pF | 110 | 110 | 110 | 110 |
| Operating Temperature Range, °C | -55 to +150 | -55 to +150 | -55 to +150 | -55 to +150 |
| Rds, on) max | 7.0 | 7.0 | 7.0 | 7.0 |
| Vgs(th) max, V | 2.0 | 2.0 | 2.0 | 2.0 |
Öko-Plan
| TN5325K1-G | TN5325N3-G | TN5325N3-G-P002 | TN5325N8-G | |
|---|---|---|---|---|
| RoHS | Compliant | Compliant | Compliant | Compliant |
Modellreihe
Serie: TN5325 (4)