Datasheet Microchip MCP3901A0-I/ML — Datenblatt

MCP3901
Two-Channel Analog Front End
Features Description Two Synchronous Sampling 16/24-bit Resolution
Delta-Sigma A/D Converters with Proprietary
Multi-Bit Architecture 91 dB SINAD, -104 dBc Total Harmonic Distortion
(THD) (up to 35th harmonic), 109 dB Spurious-free
Dynamic Range (SFDR) for Each Channel Programmable Data Rate up to 64 ksps Ultra Low-Power Shutdown mode with <2 ВµA -133 dB Crosstalk Between the Two Channels Low Drift Internal Voltage Reference: 12 ppm/В°C Differential Voltage Reference Input Pins High Gain PGA on Each Channel (up to 32 V/V) Phase Delay Compensation Between the Two
Channels with 1 Вµs time Resolution Separate Modulator Outputs for Each Channel High-Speed, Addressable 20 MHz SPI Interface
with Mode 0,0 and 1,1 Compatibility Independent Analog and Digital Power Supplies:
4.5V-5.5V AVDD, 2.7V-5.5V DVDD Low-Power Consumption: (14 mW typical at 5V) Available in Small 20-lead SSOP and QFN
Packages Industrial Temperature Ranges:
-Industrial: -40В°C to +85В°C
-Extended: -40В°C to +125В°C The MCP3901 is a dual channel Analog Front End
(AFE) containing two synchronous sampling DeltaSigma Analog-to-Digital Converters (ADC), two PGAs,
phase delay compensation block internal voltage
reference, modulator output block, and high-speed
20 MHz SPI compatible serial interface. The converters
contain a proprietary dithering algorithm for reduced
Idle tones and improved THD.
The internal register map contains 24-bit wide ADC
data words, a modulator output byte, as well as six
writable control registers to program gain,
oversampling ratio, phase, resolution, dithering, …