Datasheet Microchip PIC18LF26K83-I/SP — Datenblatt

PIC18(L)F25/26K83
28-Pin, Low-Power, High-Performance Microcontrollers
with CAN Technology
Description
The PIC18(L)FXXK83 is a full-featured CAN product family that can be used in automotive and industrial applications.
The multitude of communication peripherals found on the product family, such as CAN, SPI, two I2Cs, two UARTs, LIN,
DMX, and DALI can handle a wide range of wired and wireless (using external modules) communication protocols for
intelligent applications. This family includes a 12-bit ADC with Computation (ADC2) extensions for automated signal
analysis to reduce the complexity of the application. This, combined with the Core Independent Peripherals integration
capabilities, enables functions for motor control, power supply, sensor, signal and user interface applications. Core Features Memory • C Compiler Optimized RISC Architecture
• Operating Speed:
-Up to 64 MHz clock operation
-62.5 ns minimum instruction cycle
• Two Direct Memory Access (DMA) Controllers:
-Data transfers to SFR/GPR spaces from
either Program Flash Memory, Data
EEPROM or SFR/GPR spaces
-User-programmable source and destination
sizes
-Hardware and software-triggered data
transfers
• System Bus Arbiter with User-Configurable
Priorities for Scanner and DMA1/DMA2 with …

PIC18(L)F25/26K83
28-Pin, Low-Power, High-Performance Microcontrollers
with CAN Technology
Description
The PIC18(L)FXXK83 is a full-featured CAN product family that can be used in automotive and industrial applications.
The multitude of communication peripherals found on the product family, such as CAN, SPI, two I2Cs, two UARTs, LIN,
DMX, and DALI can handle a wide range of wired and wireless (using external modules) communication protocols for
intelligent applications. This family includes a 12-bit ADC with Computation (ADC2) extensions for automated signal
analysis to reduce the complexity of the application. This, combined with the Core Independent Peripherals integration
capabilities, enables functions for motor control, power supply, sensor, signal and user interface applications. Core Features Memory C Compiler Optimized RISC Architecture Operating Speed:
-Up to 64 MHz clock operation
-62.5 ns minimum instruction cycle Two Direct Memory Access (DMA) Controllers:
-Data transfers to SFR/GPR spaces from
either Program Flash Memory, Data
EEPROM or SFR/GPR spaces
-User-programmable source and destination
sizes
-Hardware and software-triggered data
transfers System Bus Arbiter with User-Configurable
Priorities for Scanner and DMA1/DMA2 with
respect to the main line and interrupt execution Vectored Interrupt Capability:
-Selectable high/low priority
-Fixed interrupt latency …