Datasheet Analog Devices AD4000 — Datenblatt

16-Bit, 2 MSPS/1 MSPS/500 kSPS,
Precision, Pseudo Differential, SAR ADCs
AD4000/AD4004/AD4008 Data Sheet
FEATURES and AD4008 offer 2 MSPS, 1 MSPS, and 500 kSPS throughputs,
respectively. They incorporate ease of use features that reduce
signal chain power consumption, reduce signal chain complexity,
and enable higher channel density. The high-Z mode, coupled
with a long acquisition phase, eliminates the need for a dedicated
high power, high speed ADC driver, thus broadening the range
of low power precision amplifiers that can drive these ADCs
directly while still achieving optimum performance. The input
span compression feature enables the ADC driver amplifier and
the ADC to operate off of common supply rails without the need
for a negative supply while preserving the full ADC code range.
The low serial peripheral interface (SPI) clock rate requirement
reduces the digital input/output power consumption, broadens
processor options, and simplifies the task of sending data across
digital isolation. Throughput: 2 MSPS/1 MSPS/500 kSPS options
INL: ±1.0 LSB maximum
Guaranteed 16-bit, no missing codes
Low power
9.75 mW at 2 MSPS, 4.9 mW at 1 MSPS, 2.5 mW at 500 kSPS
(VDD only) …

16-Bit, 2 MSPS/1 MSPS, Precision,
Pseudo Differential, SAR ADCs
AD4000/AD4004 Data Sheet
FEATURES GENERAL DESCRIPTION Throughput: 2 MSPS/1 MSPS options
INL: ±1.0 LSB maximum
Guaranteed 16-bit, no missing codes
Low power
9.75 mW at 2 MSPS, 4.9 mW at 1 MSPS (VDD only)
70 µW at 10 kSPS, 14 mW at 2 MSPS (total)
SNR: 93 dB typical at 1 kHz, VREF = 5 V; 90 dB typical at 100 kHz
THD: −115 dB typical at 1 kHz, VREF = 5 V; −95 dB typical at 100 kHz
Ease of use features reduce system power and complexity
Input overvoltage clamp circuit
Reduced nonlinear input charge kickback
High-Z mode
Long acquisition phase
Input span compression
Fast conversion time allows low SPI clock rates
SPI-programmable modes, read/write capability, status word
Pseudo differential (single-ended) analog input range
0 V to VREF with VREF from 2.4 V to 5.1 V
Single 1.8 V supply operation with 1.71 V to 5.5 V logic interface
SAR architecture: no latency/pipeline delay, valid first conversion …