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  Dual 60uA 10-Bit Serial DAC in MS-8 Saves Power and Space &mdash LT Journal
  PDF, 157 Kb, Datei veröffentlicht: Nov 1, 2000
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  DESIGN INFORMATION Dual 60ВµA 10-Bit Serial DAC in MS-8
  Saves Power and Space
  by Vic Schrader
  Introduction
  DACs; the data path is double buffered to allow for simultaneous
  updates. The digital inputs have
  internal Schmitt triggers, which eliminate the need for external Schmitts
  when the input signals are slow or
  noisy, such as when using optoisolators. The block diagram of the
  LTC1661 is shown in Figure 1. 3
  2.9 VREF = VCC
  CODE = 512 2.8 VCC = 5.5V 2.7 VOUT (V) The LTC1661 is a dual, serially
  addressable 10-bit, rail-to-rail voltage output DAC with Sleep mode.
  Operating on a single 2.7V–5.5V supply rail, its small size and low power
  consumption make it most appropriate for use in products with stringent
  space and/or power constraints. In
  the 8-lead MSOP package, it occupies
  just 0.02in2 of board space, 50% less
  area than a standard SO-8 package;
  each buffered DAC draws just 60ВµA
  of supply current at 5V (48ВµA at 3V).
  Sleep mode operation further reduces
  total supply-plus-reference current …

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• Data Conversion > Digital-to-Analog Converters (DAC) > Voltage Output DACs | Unipolar Digital-to-Analog Converters (DAC)

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LTC1661IMS8PBF, LTC1661IMS8 PBF