Datasheet Texas Instruments TMS320C6674 — Datenblatt

HerstellerTexas Instruments
SerieTMS320C6674
Datasheet Texas Instruments TMS320C6674

Multicore-Fest- und Gleitkomma-Digitalsignalprozessor

Datenblätter

TMS320C6674 Multicore Fixed and Floating-Point Digital Signal Processor datasheet
PDF, 2.1 Mb, Revision: E, Datei veröffentlicht: May 7, 2014
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Preise

Status

TMS320C6674ACYPTMS320C6674ACYPA
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityYesYes

Verpackung

TMS320C6674ACYPTMS320C6674ACYPA
N12
Pin841841
Package TypeCYPCYP
Package QTY4444
CarrierJEDEC TRAY (5+1)JEDEC TRAY (5+1)
Device MarkingTMS320C6674CYPTMS320C6674CYP
Width (mm)2424
Length (mm)2424
Thickness (mm)2.822.82
Mechanical DataHerunterladenHerunterladen

Parameter

Parameters / ModelsTMS320C6674ACYP
TMS320C6674ACYP
TMS320C6674ACYPA
TMS320C6674ACYPA
ApplicationsCommunications and TelecomCommunications and Telecom
DRAMDDR3DDR3
DSP4 C66x4 C66x
DSP MHz, Max.10001000
EMAC2-Port 1Gb Switch2-Port 1Gb Switch
GFLOPS64,8064,80
On-Chip L2 Cache2048 KB2048 KB
Operating Temperature Range, C-40 to 100,0 to 85-40 to 100,0 to 85
Other On-Chip Memory4096 KB4096 KB
PCI/PCIe2 PCIe Gen22 PCIe Gen2
Package Size: mm2:W x L, PKGSee datasheet (FCBGA)See datasheet (FCBGA)
RatingCatalogCatalog
Serial I/OI2C,RapidIO,SPI,TSIP,UARTI2C,RapidIO,SPI,TSIP,UART
Serial RapidIO1 (four lanes)1 (four lanes)
Total On-Chip Memory, KB65286528

Öko-Plan

TMS320C6674ACYPTMS320C6674ACYPA
RoHSCompliantCompliant

Anwendungshinweise

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    The goal of KeyStone I SerDes collateral material is to make system implementation easier for the customer by providing the system solution. For these SerDes-based interfaces, it is not assumed that the system designer is familiar with the industry specifications, SerDes technology, or RF/microwave PCB design. However, it is still expected that the PCB design work will be supervised by a knowledge
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    The initialization of the DDR3 DRAM controller on KeyStone I DSPs is straightforward as long as the proper steps are followed. However, if some steps are omitted or if some sequence-sensitive steps are implemented in the wrong order, DDR3 operation will be unpredictable.All DDR3 initialization routines must contain the basic register writes to configure the memory controller within the DSP
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    PDF, 20 Kb, Revision: A, Datei veröffentlicht: Nov 10, 2010
    The C6000 compiler tools support a new ELF-based ABI named EABI. Prior to this time, the compiler only supported a single ABI, which is now named COFF ABI. The following compelling best-in-class features are available under the C6000 EABI:GeneralZero-init globals: “int gvar;” gets set to 0 before main runs.Dynamic linking: Add code to a running system.Native ROM
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    As application complexity continues to grow, we have reached a limit on increasing performance by merely scaling clock speed. To meet the ever-increasing processing demand, modern System-On-Chip solutions contain multiple processing cores. The dilemma is how to map applications to multicore devices. In this paper, we present a programming methodology for converting applications to run on multicore
  • TI DSP Benchmarking
    PDF, 62 Kb, Datei veröffentlicht: Jan 13, 2016
    This application report provides benchmarks for the C674x DSP core, the C66x DSP core and the ARMВ®CortexВ®-A15 core. This document also shows how to reproduce these benchmarks on specific hardware platforms.
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    This application report has been compiled to provide specific information and considerations regarding thermal design requirements for all DSP and ARM-based single and multi-core processors (collectively referred to as “processors”, “System-on-chip”, or “SoC”). The information contained within this document is intended to provide a minimum level of understanding with regards to the thermal require

Modellreihe

Serie: TMS320C6674 (2)

Herstellerklassifikation

  • Semiconductors> Processors> Digital Signal Processors> C6000 DSP> C66x DSP