Datasheet Texas Instruments TMS320C6655 — Datenblatt
Hersteller | Texas Instruments |
Serie | TMS320C6655 |
Digitaler Fest- und Gleitkomma-Signalprozessor
Datenblätter
TMS320C6655 and TMS320C6657 Fixed and Floating-Point Digital Signal Processor datasheet
PDF, 1.8 Mb, Revision: C, Datei veröffentlicht: May 19, 2016
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Preise
Status
TMS320C6655CZH | TMS320C6655CZH25 | TMS320C6655CZHA | TMS320C6655CZHA25 | TMS320C6655GZHA | TMS320C6655SCZH | |
---|---|---|---|---|---|---|
Lifecycle Status | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) |
Manufacture's Sample Availability | Yes | No | No | Yes | Yes | Yes |
Verpackung
TMS320C6655CZH | TMS320C6655CZH25 | TMS320C6655CZHA | TMS320C6655CZHA25 | TMS320C6655GZHA | TMS320C6655SCZH | |
---|---|---|---|---|---|---|
N | 1 | 2 | 3 | 4 | 5 | 6 |
Pin | 625 | 625 | 625 | 625 | 625 | 625 |
Package Type | CZH | CZH | CZH | CZH | GZH | CZH |
Package QTY | 60 | 60 | 60 | 1 | 60 | |
Device Marking | TMS320C6655CZH | TMS320C6655CZH | A1GHZ | A1.25GHZ | TMS320C6655GZH | TMS320C6655SCZH |
Width (mm) | 21 | 21 | 21 | 21 | 21 | 21 |
Length (mm) | 21 | 21 | 21 | 21 | 21 | 21 |
Thickness (mm) | 2.42 | 2.42 | 2.42 | 2.42 | 2.42 | 2.42 |
Mechanical Data | Herunterladen | Herunterladen | Herunterladen | Herunterladen | Herunterladen | Herunterladen |
Carrier | JEDEC TRAY (5+1) | JEDEC TRAY (5+1) | JEDEC TRAY (5+1) | JEDEC TRAY (5+1) |
Parameter
Parameters / Models | TMS320C6655CZH | TMS320C6655CZH25 | TMS320C6655CZHA | TMS320C6655CZHA25 | TMS320C6655GZHA | TMS320C6655SCZH |
---|---|---|---|---|---|---|
Applications | Avionics & Defense,Machine Vision | Avionics & Defense,Machine Vision | Avionics & Defense,Machine Vision | Avionics & Defense,Machine Vision | Avionics & Defense,Machine Vision | Avionics & Defense,Machine Vision |
DRAM | DDR3 | DDR3 | DDR3 | DDR3 | DDR3 | DDR3 |
DSP | 1 C66x | 1 C66x | 1 C66x | 1 C66x | 1 C66x | 1 C66x |
DSP MHz, Max. | 1000,1250 | 1000,1250 | 1000,1250 | 1000,1250 | 1000,1250 | 1000,1250 |
EMAC | 10/100/1000 | 10/100/1000 | 10/100/1000 | 10/100/1000 | 10/100/1000 | 10/100/1000 |
GFLOPS | 16,20 | 16,20 | 16,20 | 16,20 | 16,20 | 16,20 |
Hardware Accelerators | VCP2,TCP3d | VCP2,TCP3d | VCP2,TCP3d | VCP2,TCP3d | VCP2,TCP3d | VCP2,TCP3d |
On-Chip L2 Cache | 1024 KB | 1024 KB | 1024 KB | 1024 KB | 1024 KB | 1024 KB |
Operating Temperature Range, C | -40 to 100,0 to 85 | -40 to 100,0 to 85 | -40 to 100,0 to 85 | -40 to 100,0 to 85 | -40 to 100,0 to 85 | -40 to 100,0 to 85 |
Other On-Chip Memory | 1024 KB | 1024 KB | 1024 KB | 1024 KB | 1024 KB | 1024 KB |
PCI/PCIe | 2 PCIe Gen2 | 2 PCIe Gen2 | 2 PCIe Gen2 | 2 PCIe Gen2 | 2 PCIe Gen2 | 2 PCIe Gen2 |
Package Size: mm2:W x L, PKG | See datasheet (FCBGA) | See datasheet (FCBGA) | See datasheet (FCBGA) | See datasheet (FCBGA) | See datasheet (FCBGA) | See datasheet (FCBGA) |
Rating | Catalog | Catalog | Catalog | Catalog | Catalog | Catalog |
Serial I/O | Hyperlink,I2C,RapidIO,SPI,TSIP,UART | Hyperlink,I2C,RapidIO,SPI,TSIP,UART | Hyperlink,I2C,RapidIO,SPI,TSIP,UART | Hyperlink,I2C,RapidIO,SPI,TSIP,UART | Hyperlink,I2C,RapidIO,SPI,TSIP,UART | Hyperlink,I2C,RapidIO,SPI,TSIP,UART |
Serial RapidIO | 1 (four lanes) | 1 (four lanes) | 1 (four lanes) | 1 (four lanes) | 1 (four lanes) | 1 (four lanes) |
Total On-Chip Memory, KB | 2278 | 2278 | 2278 | 2278 | 2278 | 2278 |
Öko-Plan
TMS320C6655CZH | TMS320C6655CZH25 | TMS320C6655CZHA | TMS320C6655CZHA25 | TMS320C6655GZHA | TMS320C6655SCZH | |
---|---|---|---|---|---|---|
RoHS | Compliant | Compliant | Compliant | Compliant | See ti.com | Compliant |
Anwendungshinweise
- TI Keystone DSP Hyperlink SerDes IBIS-AMI ModelsPDF, 3.2 Mb, Datei veröffentlicht: Oct 9, 2014
This document describes the organization, structure, and proper usage of the TI serializer and deserializer (SerDes) IBIS-AMI models for Keystone DSP Hyperlink interface. - TI Keystone DSP PCIe SerDes IBIS-AMI ModelsPDF, 4.8 Mb, Datei veröffentlicht: Oct 9, 2014
This document describes the organization, structure, and proper usage of the TI serializer and deserializer (SerDes) IBIS-AMI models for Keystone DSP PCIe interface. - SerDes Implementation Guidelines for KeyStone I DevicesPDF, 590 Kb, Datei veröffentlicht: Oct 31, 2012
The goal of KeyStone I SerDes collateral material is to make system implementation easier for the customer by providing the system solution. For these SerDes-based interfaces, it is not assumed that the system designer is familiar with the industry specifications, SerDes technology, or RF/microwave PCB design. However, it is still expected that the PCB design work will be supervised by a knowledge - KeyStone I DDR3 Initialization (Rev. E)PDF, 114 Kb, Revision: E, Datei veröffentlicht: Oct 28, 2016
The initialization of the DDR3 DRAM controller on KeyStone I DSPs is straightforward as long as the proper steps are followed. However, if some steps are omitted or if some sequence-sensitive steps are implemented in the wrong order, DDR3 operation will be unpredictable.All DDR3 initialization routines must contain the basic register writes to configure the memory controller within the DSP - TMS320C66x DSP Generation of Devices (Rev. A)PDF, 245 Kb, Revision: A, Datei veröffentlicht: Apr 25, 2011
- Hardware Design Guide for KeyStone Devices (Rev. C)PDF, 1.7 Mb, Revision: C, Datei veröffentlicht: Sep 15, 2013
- AN-1281 Bumped Die (Flip Chip) Packages (Rev. A)PDF, 2.2 Mb, Revision: A, Datei veröffentlicht: May 1, 2004
Application Note 1281 Bumped Die (Flip Chip) Packages - SERDES Link Commissioning on KeyStone I and II DevicesPDF, 138 Kb, Datei veröffentlicht: Apr 13, 2016
The serializer-deserializer (SerDes) performs serial-to-parallel conversions on data received from a peripheral device and parallel-to-serial conversion on data received from the CPU. This application report explains the SerDes transmit and receive parameters tuning, tools and some debug techniques for TI Keystone I and Keystone II devices. - PCIe Use Cases for KeyStone DevicesPDF, 320 Kb, Datei veröffentlicht: Dec 13, 2011
- The C6000 Embedded Application Binary Interface Migration Guide (Rev. A)PDF, 20 Kb, Revision: A, Datei veröffentlicht: Nov 10, 2010
The C6000 compiler tools support a new ELF-based ABI named EABI. Prior to this time, the compiler only supported a single ABI, which is now named COFF ABI. The following compelling best-in-class features are available under the C6000 EABI:GeneralZero-init globals: “int gvar;” gets set to 0 before main runs.Dynamic linking: Add code to a running system.Native ROM - Optimizing Loops on the C66x DSPPDF, 585 Kb, Datei veröffentlicht: Nov 9, 2010
- Clocking Design Guide for KeyStone DevicesPDF, 1.5 Mb, Datei veröffentlicht: Nov 9, 2010
- DDR3 Design Requirements for KeyStone Devices (Rev. B)PDF, 582 Kb, Revision: B, Datei veröffentlicht: Jun 5, 2014
- Multicore Programming Guide (Rev. B)PDF, 1.8 Mb, Revision: B, Datei veröffentlicht: Aug 29, 2012
As application complexity continues to grow, we have reached a limit on increasing performance by merely scaling clock speed. To meet the ever-increasing processing demand, modern System-On-Chip solutions contain multiple processing cores. The dilemma is how to map applications to multicore devices. In this paper, we present a programming methodology for converting applications to run on multicore - TI DSP BenchmarkingPDF, 62 Kb, Datei veröffentlicht: Jan 13, 2016
This application report provides benchmarks for the C674x DSP core, the C66x DSP core and the ARMВ®CortexВ®-A15 core. This document also shows how to reproduce these benchmarks on specific hardware platforms. - Thermal Design Guide for DSP and ARM Application Processors (Rev. A)PDF, 324 Kb, Revision: A, Datei veröffentlicht: Aug 17, 2016
This application report has been compiled to provide specific information and considerations regarding thermal design requirements for all DSP and ARM-based single and multi-core processors (collectively referred to as “processors”, “System-on-chip”, or “SoC”). The information contained within this document is intended to provide a minimum level of understanding with regards to the thermal require - Plastic Ball Grid Array [PBGA] Application Note (Rev. B)PDF, 1.6 Mb, Revision: B, Datei veröffentlicht: Aug 13, 2015
Modellreihe
Serie: TMS320C6655 (6)
Herstellerklassifikation
- Semiconductors> Processors> Digital Signal Processors> C6000 DSP> C66x DSP