Datasheet Texas Instruments TMS320C6418 — Datenblatt
| Hersteller | Texas Instruments |
| Serie | TMS320C6418 |
Digitaler Festkomma-Signalprozessor
Datenblätter
TMS320C6418 Fixed-Point Digital Signal Processor datasheet
PDF, 1.9 Mb, Revision: D, Datei veröffentlicht: Jan 17, 2006
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Preise
Status
| TMS320C6418GTS600 | TMS320C6418GTSA500 | TMS320C6418ZTS600 | TMS320C6418ZTSA500 | |
|---|---|---|---|---|
| Lifecycle Status | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No | No | No | Yes |
Verpackung
| TMS320C6418GTS600 | TMS320C6418GTSA500 | TMS320C6418ZTS600 | TMS320C6418ZTSA500 | |
|---|---|---|---|---|
| N | 1 | 2 | 3 | 4 |
| Pin | 288 | 288 | 288 | 288 |
| Package Type | GTS | GTS | ZTS | ZTS |
| Industry STD Term | FCBGA | FCBGA | FCBGA | FCBGA |
| JEDEC Code | S-PBGA-N | S-PBGA-N | S-PBGA-N | S-PBGA-N |
| Package QTY | 60 | 60 | 60 | 60 |
| Device Marking | 320C6418 | GTSA500 | TMS | ZTSA500 |
| Width (mm) | 23 | 23 | 23 | 23 |
| Length (mm) | 23 | 23 | 23 | 23 |
| Thickness (mm) | 1.9 | 1.9 | 1.9 | 1.9 |
| Pitch (mm) | 1.27 | 1.27 | 1 | 1 |
| Max Height (mm) | 2.8 | 2.8 | 2.8 | 2.8 |
| Mechanical Data | Herunterladen | Herunterladen | Herunterladen | Herunterladen |
| Carrier | JEDEC TRAY (5+1) | JEDEC TRAY (5+1) | JEDEC TRAY (5+1) |
Parameter
| Parameters / Models | TMS320C6418GTS600 | TMS320C6418GTSA500 | TMS320C6418ZTS600 | TMS320C6418ZTSA500 |
|---|---|---|---|---|
| DSP | 1 C64x | 1 C64x | ||
| Rating | Catalog | Catalog |
Öko-Plan
| TMS320C6418GTS600 | TMS320C6418GTSA500 | TMS320C6418ZTS600 | TMS320C6418ZTSA500 | |
|---|---|---|---|---|
| RoHS | See ti.com | See ti.com | Compliant | Compliant |
| Pb Free | Yes | Yes |
Anwendungshinweise
- TMS320C6418 Hardware Designer's Resource Guide (Rev. A)PDF, 205 Kb, Revision: A, Datei veröffentlicht: Oct 25, 2005
The TMS320C6418 DSP Hardware Designer's Resource Guide is a collection of the most commonly used technical documentation, and models for DSP hardware system designers. Topics covered include Getting Started, Models and Symbols, Bootloading, and Checklists to aid in your initial design and debug efforts. Each section includes pointers to valuable information including technical documentation, model - TMS320C6418 Power Consumption Summary (Rev. A)PDF, 65 Kb, Revision: A, Datei veröffentlicht: Feb 2, 2005
This document discusses the power consumption of the Texas Instruments TMS320C6418 digital signal processor (DSP). Power consumption on TMS320C64xв„ў devices is highly application-dependent. A spreadsheet is provided to model power consumption for the user's application. To get good results from the spreadsheet, realistic usage parameters must be entered. The low-core voltage and other power d - TMS320C6000 HPI Boot OperationPDF, 98 Kb, Datei veröffentlicht: Jan 6, 1999
The Texas Instruments (TI)(tm) TMS320C62x and TMS320C67x digital signal processors (DSPs) provide a variety of boot configurations that determine which actions the DSP should perform to prepare for initialization after device reset. The boot process is determined by latching the boot configuration settings at reset.The various boot processes load code from an external ROM memory space and from - TMS320C6000 EMIF to TMS320C6000 Host Port Interface (Rev. B)PDF, 372 Kb, Revision: B, Datei veröffentlicht: Sep 12, 2003
This application report describes the interface between the host port interface (HPI) and the external memory interface (EMIF) of the TMS320C6000в„ў digital signal processor (DSP). This report examines three possible pairings of the various TMS320C6000 devices: TMS320C6201/C6701 EMIF to TMS320C6201/C6701 HPI, TMS320C6211C/C6711 EMIF to TMS320C6211/C6711 HPI, and TMS320C64xв„ў EMIF to TMS3 - TMS320C6000 Multichannel Communications System InterfacePDF, 107 Kb, Datei veröffentlicht: Feb 3, 2000
This document describes a simple interface for development of multichannel telephony systems. Three interfaces are provided: 1. MVIP (Multi-Vendor Integration Protocol): Accomplished with the MT90810, Flexible MVIP Interface Circuit (FMIC). 2. T1/E1 interface: Accomplished with the PEB2254, Framing and Line Interface Component (FALC).3. Voice Band Analog Input and Output: Accomplished - Using TMS320C6416 Coprocessors: Viterbi Coprocessor (VCP) (Rev. D)PDF, 304 Kb, Revision: D, Datei veröffentlicht: Sep 15, 2003
Viterbi Coprocessor (VCP) is a programmable peripheral for decoding of convolutional codes, integrated into Texas Instruments' TMS320C6416 DSP device. The VCP is controlled via memory mapped control registers and data buffers. Control registers can be accessed directly by the CPU, whereas data buffers are typically accessed using the EDMA controller. This application note describes the relationshi - TMS320C64x EDMA ArchitecturePDF, 250 Kb, Datei veröffentlicht: Mar 3, 2004
The enhanced DMA (EDMA) controller of the TMS320C64xв„ў device is a highly efficient data transfer engine. To maximize bandwidth, minimize transfer interference, and fully utilize the resources of the EDMA, it is crucial to understand the architecture of the engine. Transfer requests (TRs) originate from many requestors, including sixty-four programmable EDMA channels, the level 2 (L2) memory - TMS320C64x EDMA Performance DataPDF, 246 Kb, Datei veröffentlicht: Mar 5, 2004
The enhanced DMA (EDMA) controller of the TMS320C64xв„ў device is a highly efficient data transfer engine, capable of maintaining transfers at up to 2.4 GB/sec at a 600 MHz CPU clock frequency. This document details measured bandwidth achieved under various operating conditions. For more information on ideal transfer bandwidth and scheduling transfers, please consult TMS320C64x EDMA Architectu - Cache Usage in High-Performance DSP Applications with the TMS320C64xPDF, 129 Kb, Datei veröffentlicht: Dec 13, 2001
The TMS320C64xв„ў, the newest member of the TMS320C6000в„ў (C6000в„ў) family, is used in high-performance DSP applications. The C64xв„ў processes information at a rate of 4800 MIPs, while operating at a clock rate of 600 MHz. Processing data at these extremely high rates requires fast memory that is directly connected to the CPU (Central Processing Unit). However, a bandwidth dilem - TMS320C64x DSP Host Port Interface (HPI) PerformancePDF, 206 Kb, Datei veröffentlicht: Oct 24, 2003
This application report describes the number of CPU cycles required to perform a given host port interface (HPI) data transfer based on a variety of permutations of burst length, CPU speed, EMIF speed, etc.The HPI provides direct connectivity between a host processor and a CPU?s memory space via a 32/16-bit parallel port. The HPI throughput between a host processor and the TMS320C64xв„ў DSP - Use and Handling of Semiconductor Packages With ENIG Pad FinishesPDF, 129 Kb, Datei veröffentlicht: Aug 31, 2004
- TMS320C6000 Enhanced DMA: Example Applications (Rev. A)PDF, 1.4 Mb, Revision: A, Datei veröffentlicht: Oct 24, 2001
The enhanced direct memory access (EDMA) controller is the backbone of the two-level cache architecture for the TMS320C6000? DSPs. The EDMA performs:o cache servicingo host-port servicingo user-programmable data transfers Through proper configuration, EDMA channels can be set up to operate continuously without requiring CPU intervention or reprogramming. This allows the CPU to use its - TMS320C6000 Host Port to MPC860 Interface (Rev. A)PDF, 311 Kb, Revision: A, Datei veröffentlicht: Jun 21, 2001
This application report describes an interface between the Motorola MPC860 microprocessor and the host port interface (HPI) of a Texas Instruments TMS320C6000в„ў (C6000в„ў) digital signal processor (DSP) device. This document includes a schematic showing connections between the two devices, PAL equations, and verification that timing requirements are met for each device (tables and timing - TMS320C6000 Host Port to MC68360 Interface (Rev. A)PDF, 261 Kb, Revision: A, Datei veröffentlicht: Sep 30, 2001
This application report describes an interface between the Motorola MC68360 quad integrated communication controller (QUICC) and the host port interface (HPI) of a TMS320C6000в„ў (C6000в„ў) digital signal processor (DSP) device. This includes a schematic showing connections between the two devices and verification that timing requirements are met for each device (tables and timing diagrams - TMS320C6000 Host Port to the i80960 Microprocessors Interface (Rev. A)PDF, 272 Kb, Revision: A, Datei veröffentlicht: Aug 31, 2001
This application report describes the interface between the Texas Instruments (TI) TMS320C6000в„ў digital signal processor (DSP) host port and the Intel 80960 microprocessor. The document includes schematics showing connections between the two devices, PAL equations, and verification that timing requirements are met for each device (tables and timing diagrams). - General Guide to Implement Logarithmic and Exponential Operations on Fixed-PointPDF, 50 Kb, Datei veröffentlicht: Jan 31, 2000
Modern audio and video compression algorithms usually take the advantage of logarithmic characteristics of human ears and eyes. This approach greatly reduces the redundancy in signals being processed. However, it poses a requirement on fixed-point DSPs to handle these logarithmic and exponential operations.This application report provides a general guide to implement these operations on fixed- - TMS320C6000 McBSP: I2S InterfacePDF, 93 Kb, Datei veröffentlicht: Sep 8, 1999
This document describes how to use the multichannel buffered serial port (McBSP) in the Texas Instruments (TI)(TM) TMS320C6000 digital signal processors (DSP) to interface with devices that conform to the Inter-IC Sound (I2S) specification. I2S is a protocol for transmitting two channels of digital audio data over a single serial connection.The flexible McBSP in the TMS320C6000 supports the I - TMS320C6000 McBSP Interface to an ST-BUS Device (Rev. B)PDF, 87 Kb, Revision: B, Datei veröffentlicht: Jun 4, 2002
This document describes how the multichannel buffered serial ports (McBSPs) in the Texas Instruments TMS320C6000в„ў digital signal processor (DSP) are used to communicate to a single-rate Serial Telecom (ST)-BUS-compliant device.The McBSP receives the framing signal, clock, and data from the ST-BUSв„ў device and processes them to generate internal frame syncs and clocks for correct data - TMS320C6000 McBSP: AC'97 Codec Interface (TLV320AIC27) (Rev. A)PDF, 289 Kb, Revision: A, Datei veröffentlicht: Jul 10, 2001
This document describes how to use the multichannel buffered serial ports (McBSPs) in the Texas Instruments TMS320C6000в„ў digital signal processor (DSP) as a digital controller for an audio codec 1997 device.The McBSP is connected to a stereo audio codec 1997 device. This application report uses the TLV320AIC27 audio codec (AIC27) as an example. The audio codec 1997 (AC'97) standard spec - TMS320C6000 Board Design for JTAG (Rev. C)PDF, 89 Kb, Revision: C, Datei veröffentlicht: Apr 2, 2002
Designing a TMS320C6000в„ў DSP board to utilize all of the functionality of the JTAG scan path is a simple process, but a few considerations must be taken into account. The default state of the emulation signals determines whether the JTAG port is used for emulation or for boundary scan. It is therefore necessary to provide flexibility in the design to accommodate those modes that are desired. - Circular Buffering on TMS320C6000 (Rev. A)PDF, 172 Kb, Revision: A, Datei veröffentlicht: Sep 12, 2000
This application report explains how circular buffering is implemented on the TMS320C6000? devices. Circular buffering helps to implement finite impulse response (FIR) filters efficiently. Filters require delay lines or buffers of past (and current) samples. Circular addressing simplifies the manipulation of pointers in accessing the data samples.This application report addresses the following - TMS320C6000 McBSP Initialization (Rev. C)PDF, 232 Kb, Revision: C, Datei veröffentlicht: Mar 8, 2004
The TMS320C6000? multichannel buffered serial port (McBSP) can operate in a variety of modes, as per application requirements. For proper operation, the serial port must be initialized in a specific order. This document describes the initialization steps necessary when either the (E)DMA or the CPU is used to service the McBSP data. Typically, the (E)DMA is used to perform read/write transfers from - Using a TMS320C6000 McBSP for Data Packing (Rev. A)PDF, 257 Kb, Revision: A, Datei veröffentlicht: Oct 31, 2001
This application report describes how to use the multichannel buffered serial port (McBSP) in the Texas Instruments TMS320C6000в„ў digital signal processor (DSP) for data packing. Data packing involves moving either multiple successive 8-bit elements to/from the McBSP as a single 16/24/32-bit element or multiple successive 16-bit words to/from the McBSP as a single 32-bit word.The McBSP - TMS320C6000 EMIF to External Asynchronous SRAM Interface (Rev. A)PDF, 118 Kb, Revision: A, Datei veröffentlicht: Aug 31, 2001
Interfacing external asynchronous static RAM (ASRAM) to the Texas Instruments (TIв„ў) TMS320C6000 series of digital signal processors (DSPs) is simple compared to previous generations of TI DSPs, thanks to the advanced external memory interface (EMIF). The EMIF provides a glueless interface to a variety of external memory devices.This document describes:EMIF control registers and ASR - TMS320C6000 McBSP as a TDM Highway (Rev. A)PDF, 313 Kb, Revision: A, Datei veröffentlicht: Sep 11, 2000
This document describes how the multichannel buffered serial ports (McBSP) in the TMS320C6000в„ў digital signal processors (DSP) are used to communicate on a time-division multiplexed (TDM) data highway.TDM provides multiple devices a time slot to perform data transfer. Thus, multiple users operate various channels; however, each user has a set of channel(s) assigned for transmission and re - TMS320C6000 u-Law and a-Law Companding with Software or the McBSPPDF, 150 Kb, Datei veröffentlicht: Feb 2, 2000
This document describes how to perform data companding with the TMS320C6000(tm)digital signal processors(DSP). Companding refers to the compression and expansion of transfer data before and after transmission, respectively.The multichannel buffered serial port (McBSP) in the TMS320C6000 supports two companding formats: mu-Law and A-Law. Both companding formats are specified in the CCITT G.711 - TMS320C6000 EMIF to External Flash Memory (Rev. A)PDF, 471 Kb, Revision: A, Datei veröffentlicht: Feb 13, 2002
Interfacing external flash memory to the Texas Instruments TMS320C6000в„ў digital signal processor (DSP) is simple compared to previous generations of TI DSPs. The TMS320C6000 advanced external memory interface (EMIF) provides a glueless interface to a variety of external memory devices.This document describes the following:EMIF control registers and asynchronous interface signals< - TMS320C6000 C Compiler: C Implementation of IntrinsicsPDF, 154 Kb, Datei veröffentlicht: Dec 7, 1999
The first optimization step that you can perform on C source code for the TMS320C62xx is to use intrinsic operators. Intrinsics are used like functions and produce assembly language statements that would otherwise be inexpressible in C. The problem is that once you have performed the first optimization step, your C source code is no longer ANSI C compatible. The code proposed within this appli - TMS320C6000 McBSP: IOM-2 Interface (Rev. A)PDF, 284 Kb, Revision: A, Datei veröffentlicht: May 21, 2001
This document describes how the multi-channel buffered serial port (McBSP) in the Texas Instruments (TI) TMS320C6000? (C6000?) digital signal processor (DSP) family is used to communicate to an ISDN Oriented Modular Interface Revision 2 (IOM-2) bus-compliant device. This document also describes the usage of McBSP registers and sample code to perform the above function. - TMS320C6000 Board Design: Considerations for Debug (Rev. C)PDF, 96 Kb, Revision: C, Datei veröffentlicht: Apr 21, 2004
- TMS320C6000 McBSP: Interface to SPI ROM (Rev. C)PDF, 99 Kb, Revision: C, Datei veröffentlicht: Jun 30, 2001
The TMS320C6000? (C6000?) Multichannel Buffered Serial Port (McBSP) is designed to interface to a device that supports synchronous Serial Peripheral Interface (SPI). This document describes the hardware interface between the McBSP and a SPI ROM. The McBSP operates as the master in a user-specified clock stop (CLKSTP) mode in order to communicate with the SPI ROM. The McBSP initialization and contr - TMS320C6000 EMIF-to-External SDRAM Interface (Rev. E)PDF, 833 Kb, Revision: E, Datei veröffentlicht: Sep 4, 2007
Interfacing external SDRAM to the Texas Instruments TMS320C6000в„ў digital signal processor (DSP) is simple, compared to previous generations of TI DSPs, because of the advanced external memory interface (EMIF). The EMIF is a glueless interface to a variety of external memory devices.This application report describes the EMIF’s control registers and SDRAM signals along with SDRAM function - TMS320C6000 Tools: Vector Table and Boot ROM Creation (Rev. D)PDF, 185 Kb, Revision: D, Datei veröffentlicht: Apr 26, 2004
Texas Instruments TMS320C6000в„ў digital signal processors (DSPs) provide a variety of boot configurations that determine which actions are performed after device reset, to prepare for initialization. The boot process is determined by latching the boot configuration settings at reset.The boot process performed by the DSP is to either load code from an external read-only memory (ROM) space - Using the TMS320C6000 McBSP as a High Speed Communication Port (Rev. A)PDF, 296 Kb, Revision: A, Datei veröffentlicht: Aug 31, 2001
This document describes how to use the mulit-channel buffered serial ports (McBSP) in the Texas Instruments (TI) TMS320C6000в„ў digital signal processor (DSP) as a high-speed data communication port.One McBSP of one C6000в„ў DSP device can be connected to a McBSP on another C6000 DSP device to serve as a high-speed data communication port. Typically, McBSPs of similar device numbers a - TMS320C6000 McBSP to Voice Band Audio Processor (VBAP) Interface (Rev. A)PDF, 240 Kb, Revision: A, Datei veröffentlicht: Jul 23, 2001
This document describes how to interface the multichannel buffered serial port (McBSP) in the TMS320C6000? digital signal processor (DSP) to a voice band audio processor (VBAP). The VBAP under discussion is the TI TLV320AC56, 3V, 2.048 MHz audio processor which is a m-law companding device. The interface is also applicable to TI?s TLV320AC57, an A-law companding audio processor.The highly - Using IBIS Models for Timing Analysis (Rev. A)PDF, 301 Kb, Revision: A, Datei veröffentlicht: Apr 15, 2003
Today?s high-speed interfaces require strict timings and accurate system design. To achieve the necessary timings for a given system, input/output buffer information specification (IBIS) models must be used. These models accurately represent the device drivers under various process conditions. Board characteristics, such as impedance, loading, length, number of nodes, etc., affect how the device d - TMS320C6000 EDMA IO Scheduling and PerformancePDF, 269 Kb, Datei veröffentlicht: Mar 5, 2004
The enhanced DMA (EDMA) is a highly efficient and parallel data transfer engine. To make the best use of its resources, it is necessary to understand the architecture and schedule transfers intelligently. This document details how to summarize, analyze, and schedule system traffic to produce efficient designs. An example audio/video system is presented and analyzed in full. Finally, EDMA performan - Thermal Considerations for the DM64xx, DM64x, and C6000 DevicesPDF, 127 Kb, Datei veröffentlicht: May 20, 2007
As integrated circuit (IC) components become more complex, the challenge of producing an end product with superior thermal performance increases. Thermal performance is a system level concern, impacted by IC packaging as well as by printed circuit board (PCB) design. This application report addresses the thermal considerations for the TMS320DM64xx, TMS320DM64x, and TMS320C6000в„ў DSP devices. - TMS320C64x to TMS320C64x+ CPU Migration Guide (Rev. A)PDF, 310 Kb, Revision: A, Datei veröffentlicht: Oct 20, 2005
This document describes migration from the Texas Instruments TMS320C64xв„ў digital signal processor (DSP) to the TMS320C64x+в„ў DSP. The objective of this document is to indicate differences between the two cores and to briefly describe new features. Functionality in the devices that is identical is not included. For detailed information about either device, see the TMS320C64x/C64x+ DSP - Introduction to TMS320C6000 DSP OptimizationPDF, 535 Kb, Datei veröffentlicht: Oct 6, 2011
The TMS320C6000™ Digital Signal Processors (DSPs) have many architectural advantages that make them ideal for computation-intensive real-time applications. However to fully leverage the architectural features that C6000™ processors offer code optimization may be required. First this document reviews five key concepts in understanding the C6000 DSP architecture and optimization. Then
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- Semiconductors> Processors> Digital Signal Processors> C6000 DSP> Other C6000 DSP