Datasheet Texas Instruments TLC5510 — Datenblatt

Hersteller	Texas Instruments
Serie	TLC5510

Datenblätter

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Status

Verpackung

Parameter

Parameters / Models	TLC5510INS	TLC5510INSLE	TLC5510INSR	TLC5510IPW	TLC5510IPWR
# Input Channels	1	1	1	1	1
Analog Input BW, MHz	14		14	14	14
Analog Input BW(MHz)		14
Approx. Price (US$)		2.59 | 1ku
Architecture	Flash	Flash	Flash	Flash	Flash
DNL(Max), +/-LSB	0.75		0.75	0.75	0.75
DNL(Max)(+/-LSB)		0.75
DNL(Typ), +/-LSB	0.3		0.3	0.3	0.3
ENOB, Bits	6.8		6.8	6.8	6.8
INL(Max), +/-LSB	1		1	1	1
INL(Max)(+/-LSB)		1
INL(Typ), +/-LSB	0.4		0.4	0.4	0.4
Input Buffer	No	No	No	No	No
Input Range, Vp-p	2	+2V	2	2	2
Interface	Parallel CMOS	Parallel CMOS	Parallel CMOS	Parallel CMOS	Parallel CMOS
Operating Temperature Range, C	-20 to 75		-20 to 75	-20 to 75	-20 to 75
Operating Temperature Range(C)		-20 to 75
Package Group	SO	SO	SO	TSSOP	TSSOP
Package Size: mm2:W x L, PKG	24SO: 117 mm2: 7.8 x 15(SO)		24SO: 117 mm2: 7.8 x 15(SO)	24TSSOP: 50 mm2: 6.4 x 7.8(TSSOP)	24TSSOP: 50 mm2: 6.4 x 7.8(TSSOP)
Package Size: mm2:W x L (PKG)		24TSSOP: 50 mm2: 6.4 x 7.8(TSSOP)
Power Consumption(Typ), mW	127.5		127.5	127.5	127.5
Power Consumption(Typ)(mW)		127.5
Rating	Catalog	Catalog	Catalog	Catalog	Catalog
Reference Mode	Ext	Ext	Ext	Ext	Ext
Resolution, Bits	8		8	8	8
Resolution(Bits)		8
SFDR, dB	42		42	42	42
SFDR(dB)		42
SINAD, dB	44		44	44	44
SNR, dB	46		46	46	46
SNR(dB)		46
Sample Rate(Max), MSPS	20		20	20	20
Sample Rate(Max)(MSPS)		20

Öko-Plan

Anwendungshinweise

• Herunterladen
  Interfacing the TLC5510 Analog-to-Digital Converter to the TMS320C203 DSP
  PDF, 401 Kb, Datei veröffentlicht: Apr 27, 2000
  This application report is a summary of the application note titled Interfacing the TLC5510 Analog-to-Digital Converter to the TMS320C203 DSP (literature number SLAA029) that presents guidelines for interfacing the TI TLC5510 analog-to-digital converter (ADC) to the TI TMS320C203 DSP. The TLC5510 is a CMOS, 8-bit, 20 MSPS (megasamples per second) ADC utilizing a semi-flash architecture. The TLC551
• Herunterladen
  Interfacing A/D Converters TLC5540/10 to the DSKplus DSP Starter Kit TMS320C54x
  PDF, 206 Kb, Datei veröffentlicht: Apr 1, 1997
  This Application Note describes the construction of a test circuit using the A/D converters TLC5540 and TLC5510, and alternative ways of interfacing these converters to the DSKplus DSP starter kit TMS320C54x. Details are given of the test circuit of the TLC5540/10 and of the interface, and the programming of the digital signal processor TMS320C54x is also described.
• Herunterladen
  Interfacing the TLC5510 Analog-to-Digital Converter to the TMS320C203 DSP
  PDF, 540 Kb, Datei veröffentlicht: Feb 1, 1998
  This application report presents guidelines for interfacing the Texas Instruments (TI(TM)) TLC5510 8-bit parallel-output analog-to-digital converter (ADC) to the TI TMS320C203 DSP data bus. The 8-bit ADC operates at a rate of 20 MHz. The C callable application program (assembly code) used to initialize the TMS320C203 and execute the code is also discussed.This report serves as reference inform
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  CDCE62005 as Clock Solution for High-Speed ADCs
  PDF, 805 Kb, Datei veröffentlicht: Sep 4, 2008
  TI has introduced a family of devices well-suited to meet the demands for high-speed ADC devices such as the ADS5527 which is capable of sampling up to 210 MSPS. To realize the full potential of these high-performance products it is imperative to provide a low phase noise clock source. The CDCE62005 clock synthesizer chip offers a real-world clocking solution to meet these stringent requirements
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  Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio
  PDF, 376 Kb, Datei veröffentlicht: Apr 28, 2009
  This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs.
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  Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)
  PDF, 327 Kb, Revision: A, Datei veröffentlicht: Sep 10, 2010
  This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir
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  Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
  PDF, 2.3 Mb, Datei veröffentlicht: Jun 2, 2008
  This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig
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  CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
  PDF, 424 Kb, Datei veröffentlicht: Jun 8, 2008
  Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers

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Herstellerklassifikation

• Semiconductors> Data Converters> Analog-to-Digital Converters (ADCs)> High Speed ADCs (>10MSPS)