Datasheet Texas Instruments THS1041 — Datenblatt
Hersteller | Texas Instruments |
Serie | THS1041 |
10-Bit-Analog-Digital-Wandler (ADC) mit 40 MSPS
Datenblätter
10-Bit, 40-MSPS Analog-to-Digital Converter With PGA and Clamp datasheet
PDF, 951 Kb, Revision: C, Datei veröffentlicht: Oct 28, 2004
Auszug aus dem Dokument
10-Bit, 40-MSPS Analog-to-Digital Converter With PGA and Clamp (Rev. C)
PDF, 955 Kb, Revision: C, Datei veröffentlicht: Oct 28, 2004
Preise
Status
THS1041CDW | THS1041CPW | THS1041CPWG4 | THS1041CPWR | THS1041CPWRG4 | THS1041IDW | THS1041IPW | THS1041IPWG4 | |
---|---|---|---|---|---|---|---|---|
Lifecycle Status | Obsolete (Manufacturer has discontinued the production of the device) | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) | Obsolete (Manufacturer has discontinued the production of the device) | Obsolete (Manufacturer has discontinued the production of the device) | Obsolete (Manufacturer has discontinued the production of the device) |
Manufacture's Sample Availability | No | No | No | No | No | No | No | No |
Verpackung
THS1041CDW | THS1041CPW | THS1041CPWG4 | THS1041CPWR | THS1041CPWRG4 | THS1041IDW | THS1041IPW | THS1041IPWG4 | |
---|---|---|---|---|---|---|---|---|
N | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |
Pin | 28 | 28 | 28 | 28 | 28 | 28 | 28 | 28 |
Package Type | DW | PW | PW | PW | PW | DW | PW | PW |
Industry STD Term | SOIC | TSSOP | TSSOP | TSSOP | TSSOP | SOIC | TSSOP | TSSOP |
JEDEC Code | R-PDSO-G | R-PDSO-G | R-PDSO-G | R-PDSO-G | R-PDSO-G | R-PDSO-G | R-PDSO-G | R-PDSO-G |
Device Marking | TH1041 | TH1041 | TH1041 | TH1041 | TH1041 | TJ1041 | TJ1041 | |
Width (mm) | 7.5 | 4.4 | 4.4 | 4.4 | 4.4 | 7.5 | 4.4 | 4.4 |
Length (mm) | 17.9 | 9.7 | 9.7 | 9.7 | 9.7 | 17.9 | 9.7 | 9.7 |
Thickness (mm) | 2.35 | 1 | 1 | 1 | 1 | 2.35 | 1 | 1 |
Pitch (mm) | 1.27 | .65 | .65 | .65 | .65 | 1.27 | .65 | .65 |
Max Height (mm) | 2.65 | 1.2 | 1.2 | 1.2 | 1.2 | 2.65 | 1.2 | 1.2 |
Mechanical Data | Herunterladen | Herunterladen | Herunterladen | Herunterladen | Herunterladen | Herunterladen | Herunterladen | Herunterladen |
Package QTY | 50 | 50 | 2000 | 2000 | ||||
Carrier | TUBE | TUBE | LARGE T&R | LARGE T&R |
Parameter
Parameters / Models | THS1041CDW | THS1041CPW | THS1041CPWG4 | THS1041CPWR | THS1041CPWRG4 | THS1041IDW | THS1041IPW | THS1041IPWG4 |
---|---|---|---|---|---|---|---|---|
# Input Channels | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
Analog Input BW, MHz | 900 | 900 | ||||||
Analog Input BW(MHz) | 900 | 900 | 900 | 900 | 900 | 900 | ||
Approx. Price (US$) | 7.46 | 1ku | 7.46 | 1ku | 7.46 | 1ku | 7.46 | 1ku | 7.46 | 1ku | 7.46 | 1ku | ||
Architecture | Pipeline | Pipeline | Pipeline | Pipeline | Pipeline | Pipeline | Pipeline | Pipeline |
DNL(Max), +/-LSB | 1 | 1 | ||||||
DNL(Max)(+/-LSB) | 1 | 1 | 1 | 1 | 1 | 1 | ||
DNL(Typ), +/-LSB | 0.3 | 0.3 | ||||||
ENOB, Bits | 9.5 | 9.5 | ||||||
ENOB(Bits) | 9.5 | 9.5 | 9.5 | 9.5 | 9.5 | 9.5 | ||
INL(Max), +/-LSB | 1.5 | 1.5 | ||||||
INL(Max)(+/-LSB) | 1.5 | 1.5 | 1.5 | 1.5 | 1.5 | 1.5 | ||
INL(Typ), +/-LSB | 0.75 | 0.75 | ||||||
Input Buffer | No | No | No | No | No | No | ||
Input Range | 2V (p-p) | 2 | 2V (p-p) | 2 | 2V (p-p) | 2V (p-p) | 2V (p-p) | 2V (p-p) |
Interface | Parallel CMOS | Parallel CMOS | Parallel CMOS | Parallel CMOS | Parallel CMOS | Parallel CMOS | Parallel CMOS | Parallel CMOS |
Operating Temperature Range, C | 0 to 70 | 0 to 70 | ||||||
Operating Temperature Range(C) | 0 to 70 | 0 to 70 | 0 to 70 | 0 to 70 | 0 to 70 | 0 to 70 | ||
Package Group | TSSOP | TSSOP | TSSOP | TSSOP | TSSOP | TSSOP | TSSOP | TSSOP |
Package Size(mm2=WxL) | 28TSSOP: 62 mm2: 6.4 x 9.7 | 28TSSOP: 62 mm2: 6.4 x 9.7 | ||||||
Package Size: mm2:W x L, PKG | 28TSSOP: 62 mm2: 6.4 x 9.7(TSSOP) | 28TSSOP: 62 mm2: 6.4 x 9.7(TSSOP) | ||||||
Package Size: mm2:W x L (PKG) | 28TSSOP: 62 mm2: 6.4 x 9.7(TSSOP) | 28TSSOP: 62 mm2: 6.4 x 9.7(TSSOP) | 28TSSOP: 62 mm2: 6.4 x 9.7(TSSOP) | 28TSSOP: 62 mm2: 6.4 x 9.7(TSSOP) | ||||
Power Consumption(Typ), mW | 103 | 103 | ||||||
Power Consumption(Typ)(mW) | 103 | 103 | 103 | 103 | 103 | 103 | ||
Rating | Catalog | Catalog | Catalog | Catalog | Catalog | Catalog | Catalog | Catalog |
Reference Mode | Ext Int | Ext,Int | Int Ext | Ext,Int | Int Ext | Ext Int | Ext Int | Ext Int |
Resolution, Bits | 10 | 10 | ||||||
Resolution(Bits) | 10 | 10 | 10 | 10 | 10 | 10 | ||
SFDR, dB | 70 | 70 | ||||||
SFDR(dB) | 70 | 70 | 70 | 70 | 70 | 70 | ||
SINAD, dB | 60 | 60 | ||||||
SINAD(dB) | 60 | 60 | 60 | 60 | 60 | 60 | ||
SNR, dB | 57 | 57 | ||||||
SNR(dB) | 57 | 57 | 57 | 57 | 57 | 57 | ||
Sample Rate (max)(SPS) | 40MSPS | 40MSPS | ||||||
Sample Rate(Max), MSPS | 40 | 40 | ||||||
Sample Rate(Max)(MSPS) | 40 | 40 | 40 | 40 |
Öko-Plan
THS1041CDW | THS1041CPW | THS1041CPWG4 | THS1041CPWR | THS1041CPWRG4 | THS1041IDW | THS1041IPW | THS1041IPWG4 | |
---|---|---|---|---|---|---|---|---|
RoHS | Not Compliant | Compliant | Compliant | Compliant | Compliant | Not Compliant | Not Compliant | Not Compliant |
Pb Free | Yes | Yes | No | No | No | No |
Anwendungshinweise
- Clamp function of high-speed ADC THS1041PDF, 235 Kb, Datei veröffentlicht: Oct 10, 2006
- High-Speed ADC THS1041and FPGA Interface ConsiderationsPDF, 130 Kb, Datei veröffentlicht: Mar 15, 2007
The Texas Instruments THS1041 is a 10-bit, 40-MSPS, high-speed analog-to-digital converter (ADC). For many years because of its low power dissipation and extended life, it has been used in various applications such as programmable gain amplifier and built-in clamp. With recent FPGA development, some application systems have been upgraded with a direct interface of the THS1041 to an FPGA, for examp - CDCE62005 as Clock Solution for High-Speed ADCsPDF, 805 Kb, Datei veröffentlicht: Sep 4, 2008
TI has introduced a family of devices well-suited to meet the demands for high-speed ADC devices such as the ADS5527 which is capable of sampling up to 210 MSPS. To realize the full potential of these high-performance products it is imperative to provide a low phase noise clock source. The CDCE62005 clock synthesizer chip offers a real-world clocking solution to meet these stringent requirements - Smart Selection of ADC/DAC Enables Better Design of Software-Defined RadioPDF, 376 Kb, Datei veröffentlicht: Apr 28, 2009
This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs. - Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)PDF, 327 Kb, Revision: A, Datei veröffentlicht: Sep 10, 2010
This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir - Phase Noise Performance and Jitter Cleaning Ability of CDCE72010PDF, 2.3 Mb, Datei veröffentlicht: Jun 2, 2008
This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig - CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital ConvertersPDF, 424 Kb, Datei veröffentlicht: Jun 8, 2008
Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers - Noise Analysis for High Speed Op Amps (Rev. A)PDF, 256 Kb, Revision: A, Datei veröffentlicht: Jan 17, 2005
As system bandwidths have increased an accurate estimate of the noise contribution for each element in the signal channel has become increasingly important. Many designers are not however particularly comfortable with the calculations required to predict the total noise for an op amp or in the conversions between the different descriptions of noise. Considerable inconsistency between manufactu - High-Speed ADC THS1041and FPGA Interface ConsiderationsPDF, 130 Kb, Datei veröffentlicht: Mar 15, 2007
The Texas Instruments THS1041 is a 10-bit, 40-MSPS, high-speed analog-to-digital converter (ADC). For many years because of its low power dissipation and extended life, it has been used in various app - Clamp function of high-speed ADC THS1041PDF, 235 Kb, Datei veröffentlicht: Oct 10, 2006
- CDCE62005 as Clock Solution for High-Speed ADCsPDF, 805 Kb, Datei veröffentlicht: Sep 4, 2008
TI has introduced a family of devices well-suited to meet the demands for high-speed ADC devices such as the ADS5527, which is capable of sampling up to 210 MSPS. To realize the full potential of thes - Smart Selection of ADC/DAC Enables Better Design of Software-Defined RadioPDF, 376 Kb, Datei veröffentlicht: Apr 28, 2009
This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs - Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)PDF, 327 Kb, Revision: A, Datei veröffentlicht: Sep 10, 2010
This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies - Phase Noise Performance and Jitter Cleaning Ability of CDCE72010PDF, 2.3 Mb, Datei veröffentlicht: Jun 2, 2008
This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the refe - CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital ConvertersPDF, 424 Kb, Datei veröffentlicht: Jun 8, 2008
Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed, high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483, which is capable of - Noise Analysis for High Speed Op Amps (Rev. A)PDF, 256 Kb, Revision: A, Datei veröffentlicht: Jan 17, 2005
As system bandwidths have increased, an accurate estimate of the noise contribution for each element in the signal channel has become increasingly important. Many designers are not, however, particula
Modellreihe
Serie: THS1041 (8)
Herstellerklassifikation
- Semiconductors> Data Converters> Analog-to-Digital Converters (ADCs)> High Speed ADCs (>10MSPS)