Datasheet Texas Instruments SN74LVTH574 — Datenblatt

Hersteller	Texas Instruments
Serie	SN74LVTH574

3.3-V ABT Octal Edge-Triggered D-Type Flip-Flops mit 3-State-Ausgängen

Datenblätter

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PDF, 1.4 Mb, Revision: G, Datei veröffentlicht: Sep 15, 2003

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Preise

Status

	SN74LVTH574DB	SN74LVTH574DBLE	SN74LVTH574DBR	SN74LVTH574DW	SN74LVTH574DWG4	SN74LVTH574DWR	SN74LVTH574NSR	SN74LVTH574PW	SN74LVTH574PWE4	SN74LVTH574PWLE	SN74LVTH574PWR	SN74LVTH574PWRG4	SN74LVTH574RGYR
Lifecycle Status	Active (Recommended for new designs)	Obsolete (Manufacturer has discontinued the production of the device)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Obsolete (Manufacturer has discontinued the production of the device)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)
Manufacture's Sample Availability	No	No	No	No	No	No	No	No	Yes	No	No	No	No

Verpackung

	SN74LVTH574DB	SN74LVTH574DBLE	SN74LVTH574DBR	SN74LVTH574DW	SN74LVTH574DWG4	SN74LVTH574DWR	SN74LVTH574NSR	SN74LVTH574PW	SN74LVTH574PWE4	SN74LVTH574PWLE	SN74LVTH574PWR	SN74LVTH574PWRG4	SN74LVTH574RGYR
N	1	2	3	4	5	6	7	8	9	10	11	12	13
Pin	20	20	20	20	20	20	20	20	20	20	20	20	20
Package Type	DB	DB	DB	DW	DW	DW	NS	PW	PW	PW	PW	PW	RGY
Industry STD Term	SSOP	SSOP	SSOP	SOIC	SOIC	SOIC	SOP	TSSOP	TSSOP	TSSOP	TSSOP	TSSOP	VQFN
JEDEC Code	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PQFP-N
Package QTY	70		2000	25	25	2000	2000	70	70		2000	2000	3000
Carrier	TUBE		LARGE T&R	TUBE	TUBE	LARGE T&R	LARGE T&R	TUBE	TUBE		LARGE T&R	LARGE T&R	LARGE T&R
Device Marking	LXH574		LXH574	LVTH574	LVTH574	LVTH574	LVTH574	LXH574	LXH574		LXH574	LXH574	LXH574
Width (mm)	5.3	5.3	5.3	7.5	7.5	7.5	5.3	4.4	4.4	4.4	4.4	4.4	3.5
Length (mm)	7.2	7.2	7.2	12.8	12.8	12.8	12.6	6.5	6.5	6.5	6.5	6.5	4.5
Thickness (mm)	1.95	1.95	1.95	2.35	2.35	2.35	1.95	1	1	1	1	1	.9
Pitch (mm)	.65	.65	.65	1.27	1.27	1.27	1.27	.65	.65	.65	.65	.65	.5
Max Height (mm)	2	2	2	2.65	2.65	2.65	2	1.2	1.2	1.2	1.2	1.2	1
Mechanical Data	Herunterladen	Herunterladen	Herunterladen	Herunterladen	Herunterladen	Herunterladen	Herunterladen	Herunterladen	Herunterladen	Herunterladen	Herunterladen	Herunterladen	Herunterladen

Parameter

Parameters / Models	SN74LVTH574DB	SN74LVTH574DBLE	SN74LVTH574DBR	SN74LVTH574DW	SN74LVTH574DWG4	SN74LVTH574DWR	SN74LVTH574NSR	SN74LVTH574PW	SN74LVTH574PWE4	SN74LVTH574PWLE	SN74LVTH574PWR	SN74LVTH574PWRG4	SN74LVTH574RGYR
3-State Output	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes
Approx. Price (US$)		0.26 \| 1ku								0.26 \| 1ku
Bits	8		8	8	8	8	8	8	8		8	8	8
Bits(#)		8								8
F @ Nom Voltage(Max), Mhz	160		160	160	160	160	160	160	160		160	160	160
F @ Nom Voltage(Max)(Mhz)		160								160
ICC @ Nom Voltage(Max), mA	5		5	5	5	5	5	5	5		5	5	5
ICC @ Nom Voltage(Max)(mA)		5								5
Input Type		TTL								TTL
Operating Temperature Range, C	-40 to 85		-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85		-40 to 85	-40 to 85	-40 to 85
Operating Temperature Range(C)		-40 to 85								-40 to 85
Output Drive (IOL/IOH)(Max), mA	64/-32		64/-32	64/-32	64/-32	64/-32	64/-32	64/-32	64/-32		64/-32	64/-32	64/-32
Output Drive (IOL/IOH)(Max)(mA)		64/-32								64/-32
Output Type		TTL								TTL
Package Group	SSOP	SSOP	SSOP	SOIC	SOIC	SOIC	SO	TSSOP	TSSOP	TSSOP	TSSOP	TSSOP	VQFN
Package Size: mm2:W x L, PKG	20SSOP: 56 mm2: 7.8 x 7.2(SSOP)		20SSOP: 56 mm2: 7.8 x 7.2(SSOP)	20SOIC: 132 mm2: 10.3 x 12.8(SOIC)	20SOIC: 132 mm2: 10.3 x 12.8(SOIC)	20SOIC: 132 mm2: 10.3 x 12.8(SOIC)	20SO: 98 mm2: 7.8 x 12.6(SO)	20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)	20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)		20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)	20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)	20VQFN: 16 mm2: 3.5 x 4.5(VQFN)
Package Size: mm2:W x L (PKG)		20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)								20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)
Rating	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog
Schmitt Trigger	No	No	No	No	No	No	No	No	No	No	No	No	No
Technology Family	LVT	LVT	LVT	LVT	LVT	LVT	LVT	LVT	LVT	LVT	LVT	LVT	LVT
VCC(Max), V	3.6		3.6	3.6	3.6	3.6	3.6	3.6	3.6		3.6	3.6	3.6
VCC(Max)(V)		3.6								3.6
VCC(Min), V	2.7		2.7	2.7	2.7	2.7	2.7	2.7	2.7		2.7	2.7	2.7
VCC(Min)(V)		2.7								2.7
Voltage(Nom), V	3.3		3.3	3.3	3.3	3.3	3.3	3.3	3.3		3.3	3.3	3.3
Voltage(Nom)(V)		3.3								3.3
tpd @ Nom Voltage(Max), ns	4.5		4.5	4.5	4.5	4.5	4.5	4.5	4.5		4.5	4.5	4.5
tpd @ Nom Voltage(Max)(ns)		4.5								4.5

Öko-Plan

	SN74LVTH574DB	SN74LVTH574DBLE	SN74LVTH574DBR	SN74LVTH574DW	SN74LVTH574DWG4	SN74LVTH574DWR	SN74LVTH574NSR	SN74LVTH574PW	SN74LVTH574PWE4	SN74LVTH574PWLE	SN74LVTH574PWR	SN74LVTH574PWRG4	SN74LVTH574RGYR
RoHS	Compliant	Not Compliant	Compliant	Compliant	Compliant	Compliant	Compliant	Compliant	Compliant	Not Compliant	Compliant	Compliant	Compliant
Pb Free	No	No

Anwendungshinweise

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LVT Family Characteristics (Rev. A)
PDF, 98 Kb, Revision: A, Datei veröffentlicht: Mar 1, 1998
To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti
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LVT-to-LVTH Conversion
PDF, 84 Kb, Datei veröffentlicht: Dec 8, 1998
Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.
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Bus-Hold Circuit
PDF, 418 Kb, Datei veröffentlicht: Feb 5, 2001
When designing systems that include CMOS devices, designers must pay special attention to the operating condition in which all of the bus drivers are in an inactive, high-impedance condition (3-state). Unless special measures are taken, this condition can lead to undefined levels and, thus, to a significant increase in the device?s power dissipation. In extreme cases, this leads to oscillation of

Modellreihe

Serie: SN74LVTH574 (13)

SN74LVTH574DB SN74LVTH574DBLE SN74LVTH574DBR SN74LVTH574DW SN74LVTH574DWG4 SN74LVTH574DWR SN74LVTH574NSR SN74LVTH574PW SN74LVTH574PWE4 SN74LVTH574PWLE SN74LVTH574PWR SN74LVTH574PWRG4 SN74LVTH574RGYR

Herstellerklassifikation

Semiconductors> Logic> Flip-Flop/Latch/Register> D-Type Flip-Flop