Datasheet Texas Instruments SN74LVTH573 — Datenblatt

Hersteller	Texas Instruments
Serie	SN74LVTH573

3.3-V ABT Octal Transparente D-Latches mit 3-Zustands-Ausgängen

Datenblätter

PDF, 1.5 Mb, Revision: H, Datei veröffentlicht: Sep 15, 2003

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	SN74LVTH573DBR	SN74LVTH573DBRE4	SN74LVTH573DW	SN74LVTH573DWE4	SN74LVTH573DWR	SN74LVTH573DWRE4	SN74LVTH573NSR	SN74LVTH573PW	SN74LVTH573PWG4	SN74LVTH573PWR	SN74LVTH573RGYR
Lifecycle Status	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)
Manufacture's Sample Availability	No	No	No	No	No	No	No	Yes	No	No	No

	SN74LVTH573DBR	SN74LVTH573DBRE4	SN74LVTH573DW	SN74LVTH573DWE4	SN74LVTH573DWR	SN74LVTH573DWRE4	SN74LVTH573NSR	SN74LVTH573PW	SN74LVTH573PWG4	SN74LVTH573PWR	SN74LVTH573RGYR
N	1	2	3	4	5	6	7	8	9	10	11
Pin	20	20	20	20	20	20	20	20	20	20	20
Package Type	DB	DB	DW	DW	DW	DW	NS	PW	PW	PW	RGY
Industry STD Term	SSOP	SSOP	SOIC	SOIC	SOIC	SOIC	SOP	TSSOP	TSSOP	TSSOP	VQFN
JEDEC Code	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PQFP-N
Package QTY	2000	2000	25	25	2000	2000	2000	70	70	2000	3000
Carrier	LARGE T&R	LARGE T&R	TUBE	TUBE	LARGE T&R	LARGE T&R	LARGE T&R	TUBE	TUBE	LARGE T&R	LARGE T&R
Device Marking	LXH573	LXH573	LVTH573	LVTH573	LVTH573	LVTH573	LVTH573	LXH573	LXH573	LXH573	LXH573
Width (mm)	5.3	5.3	7.5	7.5	7.5	7.5	5.3	4.4	4.4	4.4	3.5
Length (mm)	7.2	7.2	12.8	12.8	12.8	12.8	12.6	6.5	6.5	6.5	4.5
Thickness (mm)	1.95	1.95	2.35	2.35	2.35	2.35	1.95	1	1	1	.9
Pitch (mm)	.65	.65	1.27	1.27	1.27	1.27	1.27	.65	.65	.65	.5
Max Height (mm)	2	2	2.65	2.65	2.65	2.65	2	1.2	1.2	1.2	1
Mechanical Data	Herunterladen	Herunterladen	Herunterladen	Herunterladen	Herunterladen	Herunterladen	Herunterladen	Herunterladen	Herunterladen	Herunterladen	Herunterladen

Parameters / Models	SN74LVTH573DBR	SN74LVTH573DBRE4	SN74LVTH573DW	SN74LVTH573DWE4	SN74LVTH573DWR	SN74LVTH573DWRE4	SN74LVTH573NSR	SN74LVTH573PW	SN74LVTH573PWG4	SN74LVTH573PWR	SN74LVTH573RGYR
3-State Output	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes
Bits	8	8	8	8	8	8	8	8	8	8	8
F @ Nom Voltage(Max), Mhz	160	160	160	160	160	160	160	160	160	160	160
ICC @ Nom Voltage(Max), mA	5	5	5	5	5	5	5	5	5	5	5
Operating Temperature Range, C	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85
Output Drive (IOL/IOH)(Max), mA	64/-32	64/-32	64/-32	64/-32	64/-32	64/-32	64/-32	64/-32	64/-32	64/-32	64/-32
Package Group	SSOP	SSOP	SOIC	SOIC	SOIC	SOIC	SO	TSSOP	TSSOP	TSSOP	VQFN
Package Size: mm2:W x L, PKG	20SSOP: 56 mm2: 7.8 x 7.2(SSOP)	20SSOP: 56 mm2: 7.8 x 7.2(SSOP)	20SOIC: 132 mm2: 10.3 x 12.8(SOIC)	20SOIC: 132 mm2: 10.3 x 12.8(SOIC)	20SOIC: 132 mm2: 10.3 x 12.8(SOIC)	20SOIC: 132 mm2: 10.3 x 12.8(SOIC)	20SO: 98 mm2: 7.8 x 12.6(SO)	20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)	20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)	20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)	20VQFN: 16 mm2: 3.5 x 4.5(VQFN)
Rating	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog
Schmitt Trigger	No	No	No	No	No	No	No	No	No	No	No
Technology Family	LVT	LVT	LVT	LVT	LVT	LVT	LVT	LVT	LVT	LVT	LVT
VCC(Max), V	3.6	3.6	3.6	3.6	3.6	3.6	3.6	3.6	3.6	3.6	3.6
VCC(Min), V	2.7	2.7	2.7	2.7	2.7	2.7	2.7	2.7	2.7	2.7	2.7
Voltage(Nom), V	3.3	3.3	3.3	3.3	3.3	3.3	3.3	3.3	3.3	3.3	3.3
tpd @ Nom Voltage(Max), ns	3.9	3.9	3.9	3.9	3.9	3.9	3.9	3.9	3.9	3.9	3.9

	SN74LVTH573DBR	SN74LVTH573DBRE4	SN74LVTH573DW	SN74LVTH573DWE4	SN74LVTH573DWR	SN74LVTH573DWRE4	SN74LVTH573NSR	SN74LVTH573PW	SN74LVTH573PWG4	SN74LVTH573PWR	SN74LVTH573RGYR
RoHS	Compliant	Compliant	Compliant	Compliant	Compliant	Compliant	Compliant	Compliant	Compliant	Compliant	Compliant

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LVT Family Characteristics (Rev. A)
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To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti
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LVT-to-LVTH Conversion
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Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.
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Bus-Hold Circuit
PDF, 418 Kb, Datei veröffentlicht: Feb 5, 2001
When designing systems that include CMOS devices, designers must pay special attention to the operating condition in which all of the bus drivers are in an inactive, high-impedance condition (3-state). Unless special measures are taken, this condition can lead to undefined levels and, thus, to a significant increase in the device?s power dissipation. In extreme cases, this leads to oscillation of

Serie: SN74LVTH573 (11)