Datasheet Texas Instruments SN74LVTH543 — Datenblatt

HerstellerTexas Instruments
SerieSN74LVTH543
Datasheet Texas Instruments SN74LVTH543

3.3-V ABT Octal Registered Transceiver mit 3-State-Ausgängen

Datenblätter

SN54LVTH543, SN74LVTH543 datasheet
PDF, 872 Kb, Revision: F, Datei veröffentlicht: Oct 13, 2003
Auszug aus dem Dokument

Preise

Status

SN74LVTH543DBLESN74LVTH543DBRSN74LVTH543DWSN74LVTH543DWRSN74LVTH543PWSN74LVTH543PWLESN74LVTH543PWRSN74LVTH543PWRE4
Lifecycle StatusObsolete (Manufacturer has discontinued the production of the device)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Obsolete (Manufacturer has discontinued the production of the device)Active (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityNoNoNoNoNoNoNoNo

Verpackung

SN74LVTH543DBLESN74LVTH543DBRSN74LVTH543DWSN74LVTH543DWRSN74LVTH543PWSN74LVTH543PWLESN74LVTH543PWRSN74LVTH543PWRE4
N12345678
Pin2424242424242424
Package TypeDBDBDWDWPWPWPWPW
Industry STD TermSSOPSSOPSOICSOICTSSOPTSSOPTSSOPTSSOP
JEDEC CodeR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-G
Width (mm)5.35.37.57.54.44.44.44.4
Length (mm)8.28.215.415.47.87.87.87.8
Thickness (mm)1.951.952.352.351111
Pitch (mm).65.651.271.27.65.65.65.65
Max Height (mm)222.652.651.21.21.21.2
Mechanical DataHerunterladenHerunterladenHerunterladenHerunterladenHerunterladenHerunterladenHerunterladenHerunterladen
Package QTY20002520006020002000
CarrierLARGE T&RTUBELARGE T&RTUBELARGE T&RLARGE T&R
Device MarkingLXH543LVTH543LVTH543LXH543LXH543LXH543

Parameter

Parameters / ModelsSN74LVTH543DBLE
SN74LVTH543DBLE
SN74LVTH543DBR
SN74LVTH543DBR
SN74LVTH543DW
SN74LVTH543DW
SN74LVTH543DWR
SN74LVTH543DWR
SN74LVTH543PW
SN74LVTH543PW
SN74LVTH543PWLE
SN74LVTH543PWLE
SN74LVTH543PWR
SN74LVTH543PWR
SN74LVTH543PWRE4
SN74LVTH543PWRE4
Approx. Price (US$)0.59 | 1ku0.59 | 1ku
Bits888888
Bits(#)88
F @ Nom Voltage(Max), Mhz160160160160160160
F @ Nom Voltage(Max)(Mhz)160160
ICC @ Nom Voltage(Max), mA0.0050.0050.0050.0050.0050.005
ICC @ Nom Voltage(Max)(mA)0.0050.005
Input TypeTTL/CMOSTTL/CMOS
Operating Temperature Range, C-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85
Operating Temperature Range(C)-40 to 85-40 to 85
Output Drive (IOL/IOH)(Max), mA-32/64-32/64-32/64-32/64-32/64-32/64
Output Drive (IOL/IOH)(Max)(mA)-32/64-32/64
Output TypeLVTTLLVTTL
Package GroupSSOPSSOPSOICSOICTSSOPTSSOPTSSOPTSSOP
Package Size: mm2:W x L, PKG24SSOP: 64 mm2: 7.8 x 8.2(SSOP)24SOIC: 160 mm2: 10.3 x 15.5(SOIC)24SOIC: 160 mm2: 10.3 x 15.5(SOIC)24TSSOP: 50 mm2: 6.4 x 7.8(TSSOP)24TSSOP: 50 mm2: 6.4 x 7.8(TSSOP)24TSSOP: 50 mm2: 6.4 x 7.8(TSSOP)
Package Size: mm2:W x L (PKG)24TSSOP: 50 mm2: 6.4 x 7.8(TSSOP)24TSSOP: 50 mm2: 6.4 x 7.8(TSSOP)
RatingCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalog
Schmitt TriggerNoNoNoNoNoNoNoNo
Technology FamilyLVTLVTLVTLVTLVTLVTLVTLVT
VCC(Max), V3.63.63.63.63.63.6
VCC(Max)(V)3.63.6
VCC(Min), V2.72.72.72.72.72.7
VCC(Min)(V)2.72.7
Voltage(Nom), V3.33.33.33.33.33.3
Voltage(Nom)(V)3.33.3
tpd @ Nom Voltage(Max), ns3.73.73.73.73.73.7
tpd @ Nom Voltage(Max)(ns)3.73.7

Öko-Plan

SN74LVTH543DBLESN74LVTH543DBRSN74LVTH543DWSN74LVTH543DWRSN74LVTH543PWSN74LVTH543PWLESN74LVTH543PWRSN74LVTH543PWRE4
RoHSNot CompliantCompliantCompliantCompliantCompliantNot CompliantCompliantCompliant
Pb FreeNoNo

Anwendungshinweise

  • LVT Family Characteristics (Rev. A)
    PDF, 98 Kb, Revision: A, Datei veröffentlicht: Mar 1, 1998
    To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti
  • LVT-to-LVTH Conversion
    PDF, 84 Kb, Datei veröffentlicht: Dec 8, 1998
    Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.
  • Bus-Hold Circuit
    PDF, 418 Kb, Datei veröffentlicht: Feb 5, 2001
    When designing systems that include CMOS devices, designers must pay special attention to the operating condition in which all of the bus drivers are in an inactive, high-impedance condition (3-state). Unless special measures are taken, this condition can lead to undefined levels and, thus, to a significant increase in the device?s power dissipation. In extreme cases, this leads to oscillation of

Modellreihe

Herstellerklassifikation

  • Semiconductors> Logic> Buffer/Driver/Transceiver> Registered Transceiver