Datasheet Texas Instruments SN74LVTH373DBR — Datenblatt
| Hersteller | Texas Instruments |
| Serie | SN74LVTH373 |
| Artikelnummer | SN74LVTH373DBR |
3,3-V-ABT-Oktal-transparente D-Typ-Latches mit 3-Zustands-Ausgängen 20-SSOP -40 bis 85
Datenblätter
SN54LVTH373, SN74LVTH373 datasheet
PDF, 1.3 Mb, Revision: H, Datei veröffentlicht: Oct 13, 2003
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Preise
Status
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No |
Verpackung
| Pin | 20 |
| Package Type | DB |
| Industry STD Term | SSOP |
| JEDEC Code | R-PDSO-G |
| Package QTY | 2000 |
| Carrier | LARGE T&R |
| Device Marking | LXH373 |
| Width (mm) | 5.3 |
| Length (mm) | 7.2 |
| Thickness (mm) | 1.95 |
| Pitch (mm) | .65 |
| Max Height (mm) | 2 |
| Mechanical Data | Herunterladen |
Parameter
| 3-State Output | Yes |
| Bits | 8 |
| F @ Nom Voltage(Max) | 160 Mhz |
| ICC @ Nom Voltage(Max) | 5 mA |
| Operating Temperature Range | -40 to 85 C |
| Output Drive (IOL/IOH)(Max) | 64/-32 mA |
| Package Group | SSOP |
| Package Size: mm2:W x L | 20SSOP: 56 mm2: 7.8 x 7.2(SSOP) PKG |
| Rating | Catalog |
| Schmitt Trigger | No |
| Technology Family | LVT |
| VCC(Max) | 3.6 V |
| VCC(Min) | 2.7 V |
| Voltage(Nom) | 3.3 V |
| tpd @ Nom Voltage(Max) | 3.9 ns |
Öko-Plan
| RoHS | Compliant |
Anwendungshinweise
- LVT Family Characteristics (Rev. A)PDF, 98 Kb, Revision: A, Datei veröffentlicht: Mar 1, 1998
To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti - LVT-to-LVTH ConversionPDF, 84 Kb, Datei veröffentlicht: Dec 8, 1998
Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed. - Bus-Hold CircuitPDF, 418 Kb, Datei veröffentlicht: Feb 5, 2001
When designing systems that include CMOS devices, designers must pay special attention to the operating condition in which all of the bus drivers are in an inactive, high-impedance condition (3-state). Unless special measures are taken, this condition can lead to undefined levels and, thus, to a significant increase in the device?s power dissipation. In extreme cases, this leads to oscillation of
Modellreihe
Serie: SN74LVTH373 (11)
Herstellerklassifikation
- Semiconductors > Logic > Flip-Flop/Latch/Register > D-Type Latch