Datasheet Texas Instruments SN74LVTH273-EP — Datenblatt

HerstellerTexas Instruments
SerieSN74LVTH273-EP
Datasheet Texas Instruments SN74LVTH273-EP

Verbessertes Produkt 3.3-V Abt Octal D-Typ Flip-Flops mit Klarlack

Datenblätter

SN74LVTH273-EP datasheet
PDF, 649 Kb, Revision: A, Datei veröffentlicht: May 22, 2006
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Preise

Status

CLVTH273MNSREPG4SN74LVTH273MNSREPV62/04674-02YE
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityNoNoNo

Verpackung

CLVTH273MNSREPG4SN74LVTH273MNSREPV62/04674-02YE
N123
Pin202020
Package TypeNSNSNS
Industry STD TermSOPSOPSOP
JEDEC CodeR-PDSO-GR-PDSO-GR-PDSO-G
Package QTY200020002000
CarrierLARGE T&RLARGE T&RLARGE T&R
Device MarkingLVTH273EPLVTH273EPLVTH273EP
Width (mm)5.35.35.3
Length (mm)12.612.612.6
Thickness (mm)1.951.951.95
Pitch (mm)1.271.271.27
Max Height (mm)222
Mechanical DataHerunterladenHerunterladenHerunterladen

Parameter

Parameters / ModelsCLVTH273MNSREPG4
CLVTH273MNSREPG4
SN74LVTH273MNSREP
SN74LVTH273MNSREP
V62/04674-02YE
V62/04674-02YE
3-State OutputNoNoNo
Bits888
F @ Nom Voltage(Max), Mhz160160160
ICC @ Nom Voltage(Max), mA555
Input TypeTTLTTLTTL
Operating Temperature Range, C-55 to 125-55 to 125-55 to 125
Output Drive (IOL/IOH)(Max), mA64/-3264/-3264/-32
Output TypeTTLTTLTTL
Package GroupSOSOSO
Package Size: mm2:W x L, PKG20SO: 98 mm2: 7.8 x 12.6(SO)20SO: 98 mm2: 7.8 x 12.6(SO)20SO: 98 mm2: 7.8 x 12.6(SO)
RatingHiRel Enhanced ProductHiRel Enhanced ProductHiRel Enhanced Product
Technology FamilyLVTLVTLVT
VCC(Max), V3.63.63.6
VCC(Min), V2.72.72.7
tpd @ Nom Voltage(Max), ns4.94.94.9

Öko-Plan

CLVTH273MNSREPG4SN74LVTH273MNSREPV62/04674-02YE
RoHSCompliantCompliantCompliant

Anwendungshinweise

  • LVT Family Characteristics (Rev. A)
    PDF, 98 Kb, Revision: A, Datei veröffentlicht: Mar 1, 1998
    To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti
  • LVT-to-LVTH Conversion
    PDF, 84 Kb, Datei veröffentlicht: Dec 8, 1998
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  • 16-Bit Widebus Logic Families in 56-Ball 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)
    PDF, 895 Kb, Revision: B, Datei veröffentlicht: May 22, 2002
    TI?s 56-ball MicroStar Jr.E package registered under JEDEC MO-225 has demonstrated through modeling and experimentation that it is an optimal solution for reducing inductance and capacitance improving thermal performance and minimizing board area usage in integrated bus functions. Multiple functions released in the 56-ball MicroStar Jr.E package have superior performance characteristics compa
  • Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)
    PDF, 105 Kb, Revision: A, Datei veröffentlicht: Aug 1, 1997
    The spectrum of bus-interface devices with damping resistors or balanced/light output drive currently offered by various logic vendors is confusing at best. Inconsistencies in naming conventions and methods used for implementation make it difficult to identify the best solution for a given application. This report attempts to clarify the issue by looking at several vendors? approaches and discussi
  • Understanding Advanced Bus-Interface Products Design Guide
    PDF, 253 Kb, Datei veröffentlicht: May 1, 1996
  • Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices
    PDF, 209 Kb, Datei veröffentlicht: May 10, 2002
    Many telecom and networking applications require that cards be inserted and extracted from a live backplane without interrupting data or damaging components. To achieve this interface terminals of the card must be electrically isolated from the bus system during insertion or extraction from the backplane. To facilitate this Texas Instruments provides bus-interface and logic devices with features
  • Power-Up Behavior of Clocked Devices (Rev. A)
    PDF, 34 Kb, Revision: A, Datei veröffentlicht: Feb 6, 2015

Modellreihe

Herstellerklassifikation

  • Semiconductors> Space & High Reliability> Logic Products> Flip-Flop/Latch/Registers