Datasheet Texas Instruments SN74LVTH273 — Datenblatt

HerstellerTexas Instruments
SerieSN74LVTH273
Datasheet Texas Instruments SN74LVTH273

3,3-V ABT Octal D-Typ Flip-Flops mit Klarlack

Datenblätter

SN54LVTH273, SN74LVTH273 datasheet
PDF, 1.2 Mb, Revision: M, Datei veröffentlicht: Oct 13, 2003
Auszug aus dem Dokument

Preise

Status

SN74LVTH273DBLESN74LVTH273DBRSN74LVTH273DBRE4SN74LVTH273DWSN74LVTH273DWG4SN74LVTH273DWRSN74LVTH273DWRE4SN74LVTH273DWRG4SN74LVTH273NSRSN74LVTH273PWSN74LVTH273PWE4SN74LVTH273PWG4SN74LVTH273PWLESN74LVTH273PWRSN74LVTH273PWRE4SN74LVTH273PWRG4
Lifecycle StatusObsolete (Manufacturer has discontinued the production of the device)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Obsolete (Manufacturer has discontinued the production of the device)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityNoNoNoNoNoNoNoNoNoNoNoNoNoNoNoNo

Verpackung

SN74LVTH273DBLESN74LVTH273DBRSN74LVTH273DBRE4SN74LVTH273DWSN74LVTH273DWG4SN74LVTH273DWRSN74LVTH273DWRE4SN74LVTH273DWRG4SN74LVTH273NSRSN74LVTH273PWSN74LVTH273PWE4SN74LVTH273PWG4SN74LVTH273PWLESN74LVTH273PWRSN74LVTH273PWRE4SN74LVTH273PWRG4
N12345678910111213141516
Pin20202020202020202020202020202020
Package TypeDBDBDBDWDWDWDWDWNSPWPWPWPWPWPWPW
Industry STD TermSSOPSSOPSSOPSOICSOICSOICSOICSOICSOPTSSOPTSSOPTSSOPTSSOPTSSOPTSSOPTSSOP
JEDEC CodeR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-G
Width (mm)5.35.35.37.57.57.57.57.55.34.44.44.44.44.44.44.4
Length (mm)7.27.27.212.812.812.812.812.812.66.56.56.56.56.56.56.5
Thickness (mm)1.951.951.952.352.352.352.352.351.951111111
Pitch (mm).65.65.651.271.271.271.271.271.27.65.65.65.65.65.65.65
Max Height (mm)2222.652.652.652.652.6521.21.21.21.21.21.21.2
Mechanical DataHerunterladenHerunterladenHerunterladenHerunterladenHerunterladenHerunterladenHerunterladenHerunterladenHerunterladenHerunterladenHerunterladenHerunterladenHerunterladenHerunterladenHerunterladenHerunterladen
Package QTY2000200025252000200020002000707070200020002000
CarrierLARGE T&RLARGE T&RTUBETUBELARGE T&RLARGE T&RLARGE T&RLARGE T&RTUBETUBETUBELARGE T&RLARGE T&RLARGE T&R
Device MarkingLXH273LXH273LVTH273LVTH273LVTH273LVTH273LVTH273LVTH273LXH273LXH273LXH273LXH273LXH273LXH273

Parameter

Parameters / ModelsSN74LVTH273DBLE
SN74LVTH273DBLE
SN74LVTH273DBR
SN74LVTH273DBR
SN74LVTH273DBRE4
SN74LVTH273DBRE4
SN74LVTH273DW
SN74LVTH273DW
SN74LVTH273DWG4
SN74LVTH273DWG4
SN74LVTH273DWR
SN74LVTH273DWR
SN74LVTH273DWRE4
SN74LVTH273DWRE4
SN74LVTH273DWRG4
SN74LVTH273DWRG4
SN74LVTH273NSR
SN74LVTH273NSR
SN74LVTH273PW
SN74LVTH273PW
SN74LVTH273PWE4
SN74LVTH273PWE4
SN74LVTH273PWG4
SN74LVTH273PWG4
SN74LVTH273PWLE
SN74LVTH273PWLE
SN74LVTH273PWR
SN74LVTH273PWR
SN74LVTH273PWRE4
SN74LVTH273PWRE4
SN74LVTH273PWRG4
SN74LVTH273PWRG4
3-State OutputNoNoNoNoNoNoNoNoNoNoNoNoNoNoNoNo
Approx. Price (US$)0.26 | 1ku0.26 | 1ku
Bits88888888888888
Bits(#)88
F @ Nom Voltage(Max), Mhz160160160160160160160160160160160160160160
F @ Nom Voltage(Max)(Mhz)160160
ICC @ Nom Voltage(Max), mA55555555555555
ICC @ Nom Voltage(Max)(mA)55
Input TypeTTLTTL
Operating Temperature Range, C-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85
Operating Temperature Range(C)-40 to 85-40 to 85
Output Drive (IOL/IOH)(Max), mA64/-3264/-3264/-3264/-3264/-3264/-3264/-3264/-3264/-3264/-3264/-3264/-3264/-3264/-32
Output Drive (IOL/IOH)(Max)(mA)64/-3264/-32
Output TypeTTLTTL
Package GroupSSOPSSOPSSOPSOICSOICSOICSOICSOICSOTSSOPTSSOPTSSOPTSSOPTSSOPTSSOPTSSOP
Package Size: mm2:W x L, PKG20SSOP: 56 mm2: 7.8 x 7.2(SSOP)20SSOP: 56 mm2: 7.8 x 7.2(SSOP)20SOIC: 132 mm2: 10.3 x 12.8(SOIC)20SOIC: 132 mm2: 10.3 x 12.8(SOIC)20SOIC: 132 mm2: 10.3 x 12.8(SOIC)20SOIC: 132 mm2: 10.3 x 12.8(SOIC)20SOIC: 132 mm2: 10.3 x 12.8(SOIC)20SO: 98 mm2: 7.8 x 12.6(SO)20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)
Package Size: mm2:W x L (PKG)20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)
RatingCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalog
Schmitt TriggerNoNoNoNoNoNoNoNoNoNoNoNoNoNoNoNo
Technology FamilyLVTLVTLVTLVTLVTLVTLVTLVTLVTLVTLVTLVTLVTLVTLVTLVT
VCC(Max), V3.63.63.63.63.63.63.63.63.63.63.63.63.63.6
VCC(Max)(V)3.63.6
VCC(Min), V2.72.72.72.72.72.72.72.72.72.72.72.72.72.7
VCC(Min)(V)2.72.7
Voltage(Nom), V3.33.33.33.33.33.33.33.33.33.33.33.33.33.3
Voltage(Nom)(V)3.33.3
tpd @ Nom Voltage(Max), ns4.94.94.94.94.94.94.94.94.94.94.94.94.94.9
tpd @ Nom Voltage(Max)(ns)4.94.9

Öko-Plan

SN74LVTH273DBLESN74LVTH273DBRSN74LVTH273DBRE4SN74LVTH273DWSN74LVTH273DWG4SN74LVTH273DWRSN74LVTH273DWRE4SN74LVTH273DWRG4SN74LVTH273NSRSN74LVTH273PWSN74LVTH273PWE4SN74LVTH273PWG4SN74LVTH273PWLESN74LVTH273PWRSN74LVTH273PWRE4SN74LVTH273PWRG4
RoHSNot CompliantCompliantCompliantCompliantCompliantCompliantCompliantCompliantCompliantCompliantCompliantCompliantNot CompliantCompliantCompliantCompliant
Pb FreeNoNo

Anwendungshinweise

  • LVT Family Characteristics (Rev. A)
    PDF, 98 Kb, Revision: A, Datei veröffentlicht: Mar 1, 1998
    To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti
  • LVT-to-LVTH Conversion
    PDF, 84 Kb, Datei veröffentlicht: Dec 8, 1998
    Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.
  • Bus-Hold Circuit
    PDF, 418 Kb, Datei veröffentlicht: Feb 5, 2001
    When designing systems that include CMOS devices, designers must pay special attention to the operating condition in which all of the bus drivers are in an inactive, high-impedance condition (3-state). Unless special measures are taken, this condition can lead to undefined levels and, thus, to a significant increase in the device?s power dissipation. In extreme cases, this leads to oscillation of

Modellreihe

Herstellerklassifikation

  • Semiconductors> Logic> Flip-Flop/Latch/Register> D-Type Flip-Flop