Datasheet Texas Instruments SN74LVTH18504APMR — Datenblatt

Hersteller	Texas Instruments
Serie	SN74LVTH18504A
Artikelnummer	SN74LVTH18504APMR

3,3-V-ABT-Scan-Testgeräte mit 20-Bit-Universalbus-Transceivern 64-LQFP -40 bis 85

Datenblätter

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PDF, 923 Kb, Revision: B, Datei veröffentlicht: Jun 1, 1997

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Preise

Status

Lifecycle Status	Active (Recommended for new designs)
Manufacture's Sample Availability	No

Verpackung

Pin	64
Package Type	PM
Industry STD Term	LQFP
JEDEC Code	S-PQFP-G
Package QTY	1000
Carrier	LARGE T&R
Device Marking	LVTH18504A
Width (mm)	10
Length (mm)	10
Thickness (mm)	1.4
Pitch (mm)	.5
Max Height (mm)	1.6
Mechanical Data	Herunterladen

Parameter

Bits	20
F @ Nom Voltage(Max)	160 Mhz
ICC @ Nom Voltage(Max)	27 mA
Operating Temperature Range	-40 to 85 C
Output Drive (IOL/IOH)(Max)	64/-32 mA
Package Group	LQFP
Package Size: mm2:W x L	64LQFP: 144 mm2: 12 x 12(LQFP) PKG
Rating	Catalog
Technology Family	LVT
VCC(Max)	3.6 V
VCC(Min)	2.7 V
Voltage(Nom)	3.3 V
tpd @ Nom Voltage(Max)	5.1 ns

Öko-Plan

RoHS

Compliant

Anwendungshinweise

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This application report summarizes key information required for understanding the 'LVT8986 linking addressable scan ports (LASPs) multidrop addressable IEEE Std 1149.1 (JTAG) test access port (TAP) transceiver. This report includes information about the 'LVT8986 secondary TAPs, bypass and linking shadow protocol, scan-path description languages, serial vector format files, and an example of how to
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LVT Family Characteristics (Rev. A)
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To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti
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LVT-to-LVTH Conversion
PDF, 84 Kb, Datei veröffentlicht: Dec 8, 1998
Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.
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Bus-Hold Circuit
PDF, 418 Kb, Datei veröffentlicht: Feb 5, 2001
When designing systems that include CMOS devices, designers must pay special attention to the operating condition in which all of the bus drivers are in an inactive, high-impedance condition (3-state). Unless special measures are taken, this condition can lead to undefined levels and, thus, to a significant increase in the device?s power dissipation. In extreme cases, this leads to oscillation of

Modellreihe

Serie: SN74LVTH18504A (3)

SN74LVTH18504APM SN74LVTH18504APMG4 SN74LVTH18504APMR

Herstellerklassifikation

Semiconductors > Logic > Specialty Logic > Boundary Scan (JTAG) Logic