Datasheet Texas Instruments SN74LVTH16373 — Datenblatt

Hersteller	Texas Instruments
Serie	SN74LVTH16373

Datenblätter

Preise

Status

Verpackung

Parameter

Parameters / Models	74LVTH16373DGGRG4	74LVTH16373DLRG4	SN74LVTH16373DGGR	SN74LVTH16373DL	SN74LVTH16373DLG4	SN74LVTH16373DLR	SN74LVTH16373ZQLR	SN74LVTH16373ZRDR
3-State Output	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes
Bits	16	16	16	16	16	16	16	16
F @ Nom Voltage(Max), Mhz	160	160	160	160	160	160	160	160
ICC @ Nom Voltage(Max), mA	5	5	5	5	5	5	5	5
Operating Temperature Range, C	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85
Output Drive (IOL/IOH)(Max), mA	64/-32	64/-32	64/-32	64/-32	64/-32	64/-32	64/-32	64/-32
Package Group	TSSOP	SSOP	TSSOP	SSOP	SSOP	SSOP	BGA MICROSTAR JUNIOR	BGA MICROSTAR JUNIOR
Package Size: mm2:W x L, PKG	48TSSOP: 101 mm2: 8.1 x 12.5(TSSOP)	48SSOP: 164 mm2: 10.35 x 15.88(SSOP)	48TSSOP: 101 mm2: 8.1 x 12.5(TSSOP)	48SSOP: 164 mm2: 10.35 x 15.88(SSOP)	48SSOP: 164 mm2: 10.35 x 15.88(SSOP)	48SSOP: 164 mm2: 10.35 x 15.88(SSOP)	56BGA MICROSTAR JUNIOR: 32 mm2: 4.5 x 7(BGA MICROSTAR JUNIOR)	56BGA MICROSTAR JUNIOR: 32 mm2: 4.5 x 7(BGA MICROSTAR JUNIOR)
Rating	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog
Schmitt Trigger	No	No	No	No	No	No	No	No
Technology Family	LVT	LVT	LVT	LVT	LVT	LVT	LVT	LVT
VCC(Max), V	3.6	3.6	3.6	3.6	3.6	3.6	3.6	3.6
VCC(Min), V	2.7	2.7	2.7	2.7	2.7	2.7	2.7	2.7
Voltage(Nom), V	3.3	3.3	3.3	3.3	3.3	3.3	3.3	3.3
tpd @ Nom Voltage(Max), ns	3.8	3.8	3.8	3.8	3.8	3.8	3.8	3.8

Öko-Plan

Anwendungshinweise

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  LVT Family Characteristics (Rev. A)
  PDF, 98 Kb, Revision: A, Datei veröffentlicht: Mar 1, 1998
  To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti
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  LVT-to-LVTH Conversion
  PDF, 84 Kb, Datei veröffentlicht: Dec 8, 1998
  Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.
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  Bus-Hold Circuit
  PDF, 418 Kb, Datei veröffentlicht: Feb 5, 2001
  When designing systems that include CMOS devices, designers must pay special attention to the operating condition in which all of the bus drivers are in an inactive, high-impedance condition (3-state). Unless special measures are taken, this condition can lead to undefined levels and, thus, to a significant increase in the device?s power dissipation. In extreme cases, this leads to oscillation of
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  16-Bit Widebus Logic Families in 56-Ball 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)
  PDF, 895 Kb, Revision: B, Datei veröffentlicht: May 22, 2002
  TI?s 56-ball MicroStar Jr.E package registered under JEDEC MO-225 has demonstrated through modeling and experimentation that it is an optimal solution for reducing inductance and capacitance improving thermal performance and minimizing board area usage in integrated bus functions. Multiple functions released in the 56-ball MicroStar Jr.E package have superior performance characteristics compa
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  Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)
  PDF, 105 Kb, Revision: A, Datei veröffentlicht: Aug 1, 1997
  The spectrum of bus-interface devices with damping resistors or balanced/light output drive currently offered by various logic vendors is confusing at best. Inconsistencies in naming conventions and methods used for implementation make it difficult to identify the best solution for a given application. This report attempts to clarify the issue by looking at several vendors? approaches and discussi
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  Understanding Advanced Bus-Interface Products Design Guide
  PDF, 253 Kb, Datei veröffentlicht: May 1, 1996
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  Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices
  PDF, 209 Kb, Datei veröffentlicht: May 10, 2002
  Many telecom and networking applications require that cards be inserted and extracted from a live backplane without interrupting data or damaging components. To achieve this interface terminals of the card must be electrically isolated from the bus system during insertion or extraction from the backplane. To facilitate this Texas Instruments provides bus-interface and logic devices with features
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  Live Insertion
  PDF, 150 Kb, Datei veröffentlicht: Oct 1, 1996
  Many applications require the ability to exchange modules in electronic systems without removing the supply voltage from the module (live insertion). For example an electronic telephone exchange must always remain operational even during module maintenance and repair. To avoid damaging components additional circuitry modifications are necessary. This document describes in detail the phenomena tha
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  Input and Output Characteristics of Digital Integrated Circuits
  PDF, 1.7 Mb, Datei veröffentlicht: Oct 1, 1996
  This report contains a comprehensive collection of the input and output characteristic curves of typical integrated circuits from various logic families. These curves go beyond the information given in data sheets by providing additional details regarding the characteristics of the components. This knowledge is particularly useful when for example a decision must be made as to which circuit shou
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  Power-Up Behavior of Clocked Devices (Rev. A)
  PDF, 34 Kb, Revision: A, Datei veröffentlicht: Feb 6, 2015

Modellreihe

Herstellerklassifikation

• Semiconductors> Logic> Flip-Flop/Latch/Register> D-Type Latch