Datasheet Texas Instruments SN74LVT8980A-EP — Datenblatt

HerstellerTexas Instruments
SerieSN74LVT8980A-EP
Datasheet Texas Instruments SN74LVT8980A-EP

Erweiterte Produkt-eingebettete Testbus-Controller Ieee Std 1149.1 (Jtag) Tap Masters

Datenblätter

SN74LVT8980A-EP datasheet
PDF, 830 Kb, Revision: A, Datei veröffentlicht: Oct 29, 2003
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Preise

Status

SN74LVT8980AIDWREPV62/03668-01XE
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityNoNo

Verpackung

SN74LVT8980AIDWREPV62/03668-01XE
N12
Pin2424
Package TypeDWDW
Industry STD TermSOICSOIC
JEDEC CodeR-PDSO-GR-PDSO-G
Package QTY20002000
CarrierLARGE T&RLARGE T&R
Device MarkingLVT8980AEPLVT8980AEP
Width (mm)7.57.5
Length (mm)15.415.4
Thickness (mm)2.352.35
Pitch (mm)1.271.27
Max Height (mm)2.652.65
Mechanical DataHerunterladenHerunterladen

Parameter

Parameters / ModelsSN74LVT8980AIDWREP
SN74LVT8980AIDWREP
V62/03668-01XE
V62/03668-01XE
Bits88
ICC @ Nom Voltage(Max), mA77
Input TypeTTL/CMOSTTL/CMOS
Operating Temperature Range, C-40 to 85-40 to 85
Output Drive (IOL/IOH)(Max), mA64/-3264/-32
Output TypeLVTTLLVTTL
Package GroupSOICSOIC
Package Size: mm2:W x L, PKG24SOIC: 160 mm2: 10.3 x 15.5(SOIC)24SOIC: 160 mm2: 10.3 x 15.5(SOIC)
RatingHiRel Enhanced ProductHiRel Enhanced Product
Technology FamilyLVTLVT
VCC(Max), V3.63.6
VCC(Min), V2.72.7
tpd @ Nom Voltage(Max), ns3030

Öko-Plan

SN74LVT8980AIDWREPV62/03668-01XE
RoHSCompliantCompliant

Anwendungshinweise

  • LVT Family Characteristics (Rev. A)
    PDF, 98 Kb, Revision: A, Datei veröffentlicht: Mar 1, 1998
    To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti
  • LVT-to-LVTH Conversion
    PDF, 84 Kb, Datei veröffentlicht: Dec 8, 1998
    Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.

Modellreihe

Serie: SN74LVT8980A-EP (2)

Herstellerklassifikation

  • Semiconductors> Space & High Reliability> Logic Products> Specialty Logic Products> Boundary Scan (JTAG)