Datasheet Texas Instruments SN74LVT16543 — Datenblatt

HerstellerTexas Instruments
SerieSN74LVT16543
Datasheet Texas Instruments SN74LVT16543

Registrierte 3,3-V-ABT-16-Bit-Transceiver mit 3-Zustands-Ausgängen

Datenblätter

3.3-V ABT 16-Bit Registered Transceivers With 3-State Outputs datasheet
PDF, 825 Kb, Revision: C, Datei veröffentlicht: Jul 1, 1995
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Preise

Status

SN74LVT16543DGGRSN74LVT16543DLSN74LVT16543DLG4SN74LVT16543DLRSN74LVT16543DLRG4
Lifecycle StatusNRND (Not recommended for new designs)NRND (Not recommended for new designs)Obsolete (Manufacturer has discontinued the production of the device)NRND (Not recommended for new designs)Obsolete (Manufacturer has discontinued the production of the device)
Manufacture's Sample AvailabilityNoNoNoNoNo

Verpackung

SN74LVT16543DGGRSN74LVT16543DLSN74LVT16543DLG4SN74LVT16543DLRSN74LVT16543DLRG4
N12345
Pin5656565656
Package TypeDGGDLDLDLDL
Industry STD TermTSSOPSSOPSSOPSSOPSSOP
JEDEC CodeR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-G
Package QTY2000201000
CarrierLARGE T&RTUBELARGE T&R
Device MarkingLVT16543LVT16543LVT16543
Width (mm)6.17.497.497.497.49
Length (mm)1418.4118.4118.4118.41
Thickness (mm)1.152.592.592.592.59
Pitch (mm).5.635.635.635.635
Max Height (mm)1.22.792.792.792.79
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Öko-Plan

SN74LVT16543DGGRSN74LVT16543DLSN74LVT16543DLG4SN74LVT16543DLRSN74LVT16543DLRG4
RoHSCompliantCompliantNot CompliantCompliantNot Compliant
Pb FreeNoNo

Anwendungshinweise

  • LVT Family Characteristics (Rev. A)
    PDF, 98 Kb, Revision: A, Datei veröffentlicht: Mar 1, 1998
    To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti
  • LVT-to-LVTH Conversion
    PDF, 84 Kb, Datei veröffentlicht: Dec 8, 1998
    Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.

Modellreihe

Herstellerklassifikation

  • Semiconductors> Logic> Buffer/Driver/Transceiver> Registered Transceiver