Datasheet Texas Instruments SN74GTL2107 — Datenblatt

Hersteller	Texas Instruments
Serie	SN74GTL2107

12-Bit GTL-/GTL/GTL+ zu LVTTL Übersetzer

Datenblätter

PDF, 728 Kb, Datei veröffentlicht: Jul 1, 2006

Auszug aus dem Dokument

	SN74GTL2107PW	SN74GTL2107PWG4	SN74GTL2107PWR	SN74GTL2107PWRG4
Lifecycle Status	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)
Manufacture's Sample Availability	No	No	Yes	Yes

	SN74GTL2107PW	SN74GTL2107PWG4	SN74GTL2107PWR	SN74GTL2107PWRG4
N	1	2	3	4
Pin	28	28	28	28
Package Type	PW	PW	PW	PW
Industry STD Term	TSSOP	TSSOP	TSSOP	TSSOP
JEDEC Code	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G
Package QTY	50	50	2000	2000
Carrier	TUBE	TUBE	LARGE T&R	LARGE T&R
Device Marking	GK2107	GK2107	GK2107	GK2107
Width (mm)	4.4	4.4	4.4	4.4
Length (mm)	9.7	9.7	9.7	9.7
Thickness (mm)	1	1	1	1
Pitch (mm)	.65	.65	.65	.65
Max Height (mm)	1.2	1.2	1.2	1.2
Mechanical Data	Herunterladen	Herunterladen	Herunterladen	Herunterladen

Parameters / Models	SN74GTL2107PW	SN74GTL2107PWG4	SN74GTL2107PWR	SN74GTL2107PWRG4
Bits	12	12	12	12
F @ Nom Voltage(Max), Mhz	95	95	95	95
ICC @ Nom Voltage(Max), mA	12	12	12	12
Operating Temperature Range, C	-40 to 85	-40 to 85	-40 to 85	-40 to 85
Output Drive (IOL/IOH)(Max), mA	-16/16	-16/16	-16/16	-16/16
Package Group	TSSOP	TSSOP	TSSOP	TSSOP
Package Size: mm2:W x L, PKG	28TSSOP: 62 mm2: 6.4 x 9.7(TSSOP)	28TSSOP: 62 mm2: 6.4 x 9.7(TSSOP)	28TSSOP: 62 mm2: 6.4 x 9.7(TSSOP)	28TSSOP: 62 mm2: 6.4 x 9.7(TSSOP)
Rating	Catalog	Catalog	Catalog	Catalog
Schmitt Trigger	No	No	No	No
Technology Family	GTL	GTL	GTL	GTL
VCC(Max), V	3.6	3.6	3.6	3.6
VCC(Min), V	3	3	3	3
Voltage(Nom), V	3.3	3.3	3.3	3.3
tpd @ Nom Voltage(Max), ns	10	10	10	10

	SN74GTL2107PW	SN74GTL2107PWG4	SN74GTL2107PWR	SN74GTL2107PWRG4
RoHS	Compliant	Compliant	Compliant	Compliant

Herunterladen
GTL/BTL: A Low-Swing Solution for High-Speed Digital Logic (Rev. A)
PDF, 184 Kb, Revision: A, Datei veröffentlicht: Mar 1, 1997
GTL and BTL transceivers provide high-performance, excellent signal integrity and cost-effectiveness in high-speed backplane and point-to-point applications. This document discusses the GTL and BTL devices input/output (I/O) structure, power consumption, simultaneous switching, slew rate, and signal integrity. Design considerations for using these devices are provided.
Herunterladen
Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices
PDF, 209 Kb, Datei veröffentlicht: May 10, 2002
Many telecom and networking applications require that cards be inserted and extracted from a live backplane without interrupting data or damaging components. To achieve this interface terminals of the card must be electrically isolated from the bus system during insertion or extraction from the backplane. To facilitate this Texas Instruments provides bus-interface and logic devices with features

Serie: SN74GTL2107 (4)