Datasheet Texas Instruments SN74ALVCH373 — Datenblatt

HerstellerTexas Instruments
SerieSN74ALVCH373
Datasheet Texas Instruments SN74ALVCH373

Octal Transparent D-Type Latch mit 3-State-Ausgängen

Datenblätter

SN74ALVCH373 datasheet
PDF, 1.1 Mb, Revision: H, Datei veröffentlicht: Sep 2, 2004
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Preise

Status

SN74ALVCH373DGVRSN74ALVCH373DWSN74ALVCH373DWRSN74ALVCH373PWRSN74ALVCH373PWRE4SN74ALVCH373PWRG4SN74ALVCH373ZQNR
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityNoNoNoNoNoNoNo

Verpackung

SN74ALVCH373DGVRSN74ALVCH373DWSN74ALVCH373DWRSN74ALVCH373PWRSN74ALVCH373PWRE4SN74ALVCH373PWRG4SN74ALVCH373ZQNR
N1234567
Pin20202020202020
Package TypeDGVDWDWPWPWPWZQN
Industry STD TermTVSOPSOICSOICTSSOPTSSOPTSSOPBGA MICROSTAR JUNIOR
JEDEC CodeR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PBGA-N
Package QTY20002520002000200020001000
CarrierLARGE T&RTUBELARGE T&RLARGE T&RLARGE T&RLARGE T&RLARGE T&R
Device MarkingVB373ALVCH373ALVCH373VB373VB373VB373VB373
Width (mm)4.47.57.54.44.44.43
Length (mm)512.812.86.56.56.54
Thickness (mm)1.052.352.35111.75
Pitch (mm).41.271.27.65.65.65.65
Max Height (mm)1.22.652.651.21.21.21
Mechanical DataHerunterladenHerunterladenHerunterladenHerunterladenHerunterladenHerunterladenHerunterladen

Parameter

Parameters / ModelsSN74ALVCH373DGVR
SN74ALVCH373DGVR
SN74ALVCH373DW
SN74ALVCH373DW
SN74ALVCH373DWR
SN74ALVCH373DWR
SN74ALVCH373PWR
SN74ALVCH373PWR
SN74ALVCH373PWRE4
SN74ALVCH373PWRE4
SN74ALVCH373PWRG4
SN74ALVCH373PWRG4
SN74ALVCH373ZQNR
SN74ALVCH373ZQNR
3-State OutputYesYesYesYesYesYesYes
Bits8888888
F @ Nom Voltage(Max), Mhz150150150150150150150
ICC @ Nom Voltage(Max), mA0.020.020.020.020.020.020.02
Operating Temperature Range, C-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85
Output Drive (IOL/IOH)(Max), mA24/-2424/-2424/-2424/-2424/-2424/-2424/-24
Package GroupTVSOPSOICSOICTSSOPTSSOPTSSOPBGA MICROSTAR JUNIOR
Package Size: mm2:W x L, PKG20TVSOP: 32 mm2: 6.4 x 5(TVSOP)20SOIC: 132 mm2: 10.3 x 12.8(SOIC)20SOIC: 132 mm2: 10.3 x 12.8(SOIC)20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)20BGA MICROSTAR JUNIOR: 12 mm2: 3 x 4(BGA MICROSTAR JUNIOR)
RatingCatalogCatalogCatalogCatalogCatalogCatalogCatalog
Schmitt TriggerNoNoNoNoNoNoNo
Technology FamilyALVCALVCALVCALVCALVCALVCALVC
VCC(Max), V3.63.63.63.63.63.63.6
VCC(Min), V1.651.651.651.651.651.651.65
Voltage(Nom), V1.8,2.5,2.7,3.31.8,2.5,2.7,3.31.8,2.5,2.7,3.31.8,2.5,2.7,3.31.8,2.5,2.7,3.31.8,2.5,2.7,3.31.8,2.5,2.7,3.3
tpd @ Nom Voltage(Max), ns6.3,4,3.66.3,4,3.66.3,4,3.66.3,4,3.66.3,4,3.66.3,4,3.66.3,4,3.6

Öko-Plan

SN74ALVCH373DGVRSN74ALVCH373DWSN74ALVCH373DWRSN74ALVCH373PWRSN74ALVCH373PWRE4SN74ALVCH373PWRG4SN74ALVCH373ZQNR
RoHSCompliantCompliantCompliantCompliantCompliantCompliantCompliant

Anwendungshinweise

  • TI SN74ALVC16835 Component Specification Analysis for PC100
    PDF, 43 Kb, Datei veröffentlicht: Aug 3, 1998
    The PC100 standard establishes design parameters for the PC SDRAM DIMM that is designed to operate at 100 MHz. The 168-pin, 8-byte, registered SDRAM DIMM is a JEDEC-defined device (JC-42.5-96-146A). Some of the defined signal paths include data signals, address signals, and control signals. This application report discusses the SN74ALVC16835 18-bit universal bus driver that is available from T
  • Logic Solutions for PC-100 SDRAM Registered DIMMs (Rev. A)
    PDF, 96 Kb, Revision: A, Datei veröffentlicht: May 13, 1998
    Design of high-performance personal computer (PC) systems that are capable of meeting the needs imposed by modern operating systems and software includes the use of large banks of SDRAMs on DIMMs (see Figure 1).To meet the demands of stable functionality over the broad spectrum of operating environments, meet system timing needs, and to support data integrity, the loads presented by the large
  • Bus-Hold Circuit
    PDF, 418 Kb, Datei veröffentlicht: Feb 5, 2001
    When designing systems that include CMOS devices, designers must pay special attention to the operating condition in which all of the bus drivers are in an inactive, high-impedance condition (3-state). Unless special measures are taken, this condition can lead to undefined levels and, thus, to a significant increase in the device?s power dissipation. In extreme cases, this leads to oscillation of
  • 16-Bit Widebus Logic Families in 56-Ball 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)
    PDF, 895 Kb, Revision: B, Datei veröffentlicht: May 22, 2002
    TI?s 56-ball MicroStar Jr.E package registered under JEDEC MO-225 has demonstrated through modeling and experimentation that it is an optimal solution for reducing inductance and capacitance improving thermal performance and minimizing board area usage in integrated bus functions. Multiple functions released in the 56-ball MicroStar Jr.E package have superior performance characteristics compa
  • Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A)
    PDF, 154 Kb, Revision: A, Datei veröffentlicht: Sep 8, 1999
    In the last few years the trend toward reducing supply voltage (VCC) has continued as reflected in an additional specification of 2.5-V VCC for the AVC ALVT ALVC LVC LV and the CBTLV families.In this application report the different logic levels at VCC of 5 V 3.3 V 2.5 V and 1.8 V are compared. Within the report the possibilities for migration from 5-V logic and 3.3-V logic families

Modellreihe

Herstellerklassifikation

  • Semiconductors> Logic> Flip-Flop/Latch/Register> D-Type Latch