Datasheet Texas Instruments SN74ALVCH162260 — Datenblatt

HerstellerTexas Instruments
SerieSN74ALVCH162260
Datasheet Texas Instruments SN74ALVCH162260

12-Bit- bis 24-Bit-Multiplex-D-Typ-Latch mit 3-Zustands-Ausgängen

Datenblätter

SN74ALVCH162260 datasheet
PDF, 352 Kb, Revision: I, Datei veröffentlicht: Aug 5, 2004
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Preise

Status

74ALVCH162260DLRG474ALVCH162260GRG4SN74ALVCH162260DLSN74ALVCH162260DLRSN74ALVCH162260GR
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityNoNoNoNoNo

Verpackung

74ALVCH162260DLRG474ALVCH162260GRG4SN74ALVCH162260DLSN74ALVCH162260DLRSN74ALVCH162260GR
N12345
Pin5656565656
Package TypeDLDGGDLDLDGG
Industry STD TermSSOPTSSOPSSOPSSOPTSSOP
JEDEC CodeR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-G
Package QTY100020002010002000
CarrierLARGE T&RLARGE T&RTUBELARGE T&RLARGE T&R
Device MarkingALVCH162260ALVCH162260ALVCH162260ALVCH162260ALVCH162260
Width (mm)7.496.17.497.496.1
Length (mm)18.411418.4118.4114
Thickness (mm)2.591.152.592.591.15
Pitch (mm).635.5.635.635.5
Max Height (mm)2.791.22.792.791.2
Mechanical DataHerunterladenHerunterladenHerunterladenHerunterladenHerunterladen

Parameter

Parameters / Models74ALVCH162260DLRG4
74ALVCH162260DLRG4
74ALVCH162260GRG4
74ALVCH162260GRG4
SN74ALVCH162260DL
SN74ALVCH162260DL
SN74ALVCH162260DLR
SN74ALVCH162260DLR
SN74ALVCH162260GR
SN74ALVCH162260GR
3-State OutputYesYesYesYesYes
Bits1212121212
F @ Nom Voltage(Max), Mhz150150150150150
ICC @ Nom Voltage(Max), mA0.040.040.040.040.04
Operating Temperature Range, C-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85
Output Drive (IOL/IOH)(Max), mA24/-2424/-2424/-2424/-2424/-24
Package GroupSSOPTSSOPSSOPSSOPTSSOP
Package Size: mm2:W x L, PKG56SSOP: 191 mm2: 10.35 x 18.42(SSOP)56TSSOP: 113 mm2: 8.1 x 14(TSSOP)56SSOP: 191 mm2: 10.35 x 18.42(SSOP)56SSOP: 191 mm2: 10.35 x 18.42(SSOP)56TSSOP: 113 mm2: 8.1 x 14(TSSOP)
RatingCatalogCatalogCatalogCatalogCatalog
Schmitt TriggerNoNoNoNoNo
Technology FamilyALVCALVCALVCALVCALVC
VCC(Max), V3.63.63.63.63.6
VCC(Min), V1.651.651.651.651.65
Voltage(Nom), V1.8,2.5,2.7,3.31.8,2.5,2.7,3.31.8,2.5,2.7,3.31.8,2.5,2.7,3.31.8,2.5,2.7,3.3
tpd @ Nom Voltage(Max), ns5.9,5.8,4.95.9,5.8,4.95.9,5.8,4.95.9,5.8,4.95.9,5.8,4.9

Öko-Plan

74ALVCH162260DLRG474ALVCH162260GRG4SN74ALVCH162260DLSN74ALVCH162260DLRSN74ALVCH162260GR
RoHSCompliantCompliantCompliantCompliantCompliant

Anwendungshinweise

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    PDF, 43 Kb, Datei veröffentlicht: Aug 3, 1998
    The PC100 standard establishes design parameters for the PC SDRAM DIMM that is designed to operate at 100 MHz. The 168-pin, 8-byte, registered SDRAM DIMM is a JEDEC-defined device (JC-42.5-96-146A). Some of the defined signal paths include data signals, address signals, and control signals. This application report discusses the SN74ALVC16835 18-bit universal bus driver that is available from T
  • Logic Solutions for PC-100 SDRAM Registered DIMMs (Rev. A)
    PDF, 96 Kb, Revision: A, Datei veröffentlicht: May 13, 1998
    Design of high-performance personal computer (PC) systems that are capable of meeting the needs imposed by modern operating systems and software includes the use of large banks of SDRAMs on DIMMs (see Figure 1).To meet the demands of stable functionality over the broad spectrum of operating environments, meet system timing needs, and to support data integrity, the loads presented by the large
  • Bus-Hold Circuit
    PDF, 418 Kb, Datei veröffentlicht: Feb 5, 2001
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  • Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A)
    PDF, 154 Kb, Revision: A, Datei veröffentlicht: Sep 8, 1999
    In the last few years the trend toward reducing supply voltage (VCC) has continued as reflected in an additional specification of 2.5-V VCC for the AVC ALVT ALVC LVC LV and the CBTLV families.In this application report the different logic levels at VCC of 5 V 3.3 V 2.5 V and 1.8 V are compared. Within the report the possibilities for migration from 5-V logic and 3.3-V logic families
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    PDF, 105 Kb, Revision: A, Datei veröffentlicht: Aug 1, 1997
    The spectrum of bus-interface devices with damping resistors or balanced/light output drive currently offered by various logic vendors is confusing at best. Inconsistencies in naming conventions and methods used for implementation make it difficult to identify the best solution for a given application. This report attempts to clarify the issue by looking at several vendors? approaches and discussi
  • Understanding Advanced Bus-Interface Products Design Guide
    PDF, 253 Kb, Datei veröffentlicht: May 1, 1996
  • Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices
    PDF, 115 Kb, Datei veröffentlicht: Dec 1, 1997
    This application report explores the possibilities for migrating to 3.3-V and 2.5-V power supplies and discusses the implications.Customers are successfully using a wide range of low-voltage 3.3-V logic devices. These devices are within Texas Instruments (TI) advanced low-voltage CMOS (ALVC) crossbar technology (CBT) crossbar technology with integrated diode (CBTD) low-voltage crossbar techn
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    PDF, 150 Kb, Datei veröffentlicht: Oct 1, 1996
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    PDF, 89 Kb, Revision: B, Datei veröffentlicht: Jun 1, 1997
    Reduction of power consumption makes a device more reliable. The need for devices that consume a minimum amount of power was a major driving force behind the development of CMOS technologies. As a result CMOS devices are best known for low power consumption. However for minimizing the power requirements of a board or a system simply knowing that CMOS devices may use less power than equivale
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    PDF, 1.7 Mb, Datei veröffentlicht: Oct 1, 1996
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  • Power-Up Behavior of Clocked Devices (Rev. A)
    PDF, 34 Kb, Revision: A, Datei veröffentlicht: Feb 6, 2015

Modellreihe

Herstellerklassifikation

  • Semiconductors> Logic> Flip-Flop/Latch/Register> D-Type Latch