Datasheet Texas Instruments SN74ALVC245 — Datenblatt

HerstellerTexas Instruments
SerieSN74ALVC245
Datasheet Texas Instruments SN74ALVC245

Oktalbus-Transceiver mit 3-Zustands-Ausgängen

Datenblätter

SN74ALVC245 datasheet
PDF, 1.3 Mb, Revision: D, Datei veröffentlicht: Jul 27, 2004
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Preise

Status

SN74ALVC245DGVRSN74ALVC245DWSN74ALVC245DWRSN74ALVC245NSRSN74ALVC245PWSN74ALVC245PWG4SN74ALVC245PWRSN74ALVC245PWRE4SN74ALVC245PWRG4SN74ALVC245RGYRSN74ALVC245RGYRG4
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityNoYesNoNoNoNoNoYesNoNoNo

Verpackung

SN74ALVC245DGVRSN74ALVC245DWSN74ALVC245DWRSN74ALVC245NSRSN74ALVC245PWSN74ALVC245PWG4SN74ALVC245PWRSN74ALVC245PWRE4SN74ALVC245PWRG4SN74ALVC245RGYRSN74ALVC245RGYRG4
N1234567891011
Pin2020202020202020202020
Package TypeDGVDWDWNSPWPWPWPWPWRGYRGY
Industry STD TermTVSOPSOICSOICSOPTSSOPTSSOPTSSOPTSSOPTSSOPVQFNVQFN
JEDEC CodeR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PQFP-NR-PQFP-N
Package QTY20002520002000707020002000200030003000
CarrierLARGE T&RTUBELARGE T&RLARGE T&RTUBETUBELARGE T&RLARGE T&RLARGE T&RLARGE T&RLARGE T&R
Device MarkingVA245ALVC245ALVC245ALVC245VA245VA245VA245VA245VA245VA245VA245
Width (mm)4.47.57.55.34.44.44.44.44.43.53.5
Length (mm)512.812.812.66.56.56.56.56.54.54.5
Thickness (mm)1.052.352.351.9511111.9.9
Pitch (mm).41.271.271.27.65.65.65.65.65.5.5
Max Height (mm)1.22.652.6521.21.21.21.21.211
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Parameter

Parameters / ModelsSN74ALVC245DGVR
SN74ALVC245DGVR
SN74ALVC245DW
SN74ALVC245DW
SN74ALVC245DWR
SN74ALVC245DWR
SN74ALVC245NSR
SN74ALVC245NSR
SN74ALVC245PW
SN74ALVC245PW
SN74ALVC245PWG4
SN74ALVC245PWG4
SN74ALVC245PWR
SN74ALVC245PWR
SN74ALVC245PWRE4
SN74ALVC245PWRE4
SN74ALVC245PWRG4
SN74ALVC245PWRG4
SN74ALVC245RGYR
SN74ALVC245RGYR
SN74ALVC245RGYRG4
SN74ALVC245RGYRG4
Bits88888888888
F @ Nom Voltage(Max), Mhz100100100100100100100100100100100
ICC @ Nom Voltage(Max), mA0.010.010.010.010.010.010.010.010.010.010.01
Operating Temperature Range, C-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85
Output Drive (IOL/IOH)(Max), mA-24/24-24/24-24/24-24/24-24/24-24/24-24/24-24/24-24/24-24/24-24/24
Package GroupTVSOPSOICSOICSOTSSOPTSSOPTSSOPTSSOPTSSOPVQFNVQFN
Package Size: mm2:W x L, PKG20TVSOP: 32 mm2: 6.4 x 5(TVSOP)20SOIC: 132 mm2: 10.3 x 12.8(SOIC)20SOIC: 132 mm2: 10.3 x 12.8(SOIC)20SO: 98 mm2: 7.8 x 12.6(SO)20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)20VQFN: 16 mm2: 3.5 x 4.5(VQFN)20VQFN: 16 mm2: 3.5 x 4.5(VQFN)
RatingCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalog
Schmitt TriggerNoNoNoNoNoNoNoNoNoNoNo
Technology FamilyALVCALVCALVCALVCALVCALVCALVCALVCALVCALVCALVC
VCC(Max), V3.63.63.63.63.63.63.63.63.63.63.6
VCC(Min), V1.651.651.651.651.651.651.651.651.651.651.65
Voltage(Nom), V1.8,2.5,2.7,3.31.8,2.5,2.7,3.31.8,2.5,2.7,3.31.8,2.5,2.7,3.31.8,2.5,2.7,3.31.8,2.5,2.7,3.31.8,2.5,2.7,3.31.8,2.5,2.7,3.31.8,2.5,2.7,3.31.8,2.5,2.7,3.31.8,2.5,2.7,3.3
tpd @ Nom Voltage(Max), ns3.4,5.53.4,5.53.4,5.53.4,5.53.4,5.53.4,5.53.4,5.53.4,5.53.4,5.53.4,5.53.4,5.5

Öko-Plan

SN74ALVC245DGVRSN74ALVC245DWSN74ALVC245DWRSN74ALVC245NSRSN74ALVC245PWSN74ALVC245PWG4SN74ALVC245PWRSN74ALVC245PWRE4SN74ALVC245PWRG4SN74ALVC245RGYRSN74ALVC245RGYRG4
RoHSCompliantCompliantCompliantCompliantCompliantCompliantCompliantCompliantCompliantCompliantCompliant

Anwendungshinweise

  • TI SN74ALVC16835 Component Specification Analysis for PC100
    PDF, 43 Kb, Datei veröffentlicht: Aug 3, 1998
    The PC100 standard establishes design parameters for the PC SDRAM DIMM that is designed to operate at 100 MHz. The 168-pin, 8-byte, registered SDRAM DIMM is a JEDEC-defined device (JC-42.5-96-146A). Some of the defined signal paths include data signals, address signals, and control signals. This application report discusses the SN74ALVC16835 18-bit universal bus driver that is available from T
  • Logic Solutions for PC-100 SDRAM Registered DIMMs (Rev. A)
    PDF, 96 Kb, Revision: A, Datei veröffentlicht: May 13, 1998
    Design of high-performance personal computer (PC) systems that are capable of meeting the needs imposed by modern operating systems and software includes the use of large banks of SDRAMs on DIMMs (see Figure 1).To meet the demands of stable functionality over the broad spectrum of operating environments, meet system timing needs, and to support data integrity, the loads presented by the large
  • 16-Bit Widebus Logic Families in 56-Ball 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)
    PDF, 895 Kb, Revision: B, Datei veröffentlicht: May 22, 2002
    TI?s 56-ball MicroStar Jr.E package registered under JEDEC MO-225 has demonstrated through modeling and experimentation that it is an optimal solution for reducing inductance and capacitance improving thermal performance and minimizing board area usage in integrated bus functions. Multiple functions released in the 56-ball MicroStar Jr.E package have superior performance characteristics compa
  • Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A)
    PDF, 154 Kb, Revision: A, Datei veröffentlicht: Sep 8, 1999
    In the last few years the trend toward reducing supply voltage (VCC) has continued as reflected in an additional specification of 2.5-V VCC for the AVC ALVT ALVC LVC LV and the CBTLV families.In this application report the different logic levels at VCC of 5 V 3.3 V 2.5 V and 1.8 V are compared. Within the report the possibilities for migration from 5-V logic and 3.3-V logic families

Modellreihe

Herstellerklassifikation

  • Semiconductors> Logic> Buffer/Driver/Transceiver> Standard Transceiver