Datasheet Texas Instruments SN74ALVC126 — Datenblatt

Hersteller	Texas Instruments
Serie	SN74ALVC126

Vierfach-Buspuffer-Gate mit 3-Zustands-Ausgängen

Datenblätter

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PDF, 651 Kb, Revision: J, Datei veröffentlicht: Sep 17, 2004

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Preise

Status

	SN74ALVC126D	SN74ALVC126DGVR	SN74ALVC126DGVRE4	SN74ALVC126DR	SN74ALVC126NSR	SN74ALVC126PWR	SN74ALVC126PWRE4	SN74ALVC126PWRG4
Lifecycle Status	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)
Manufacture's Sample Availability	No	No	No	No	No	No	No	No

Verpackung

	SN74ALVC126D	SN74ALVC126DGVR	SN74ALVC126DGVRE4	SN74ALVC126DR	SN74ALVC126NSR	SN74ALVC126PWR	SN74ALVC126PWRE4	SN74ALVC126PWRG4
N	1	2	3	4	5	6	7	8
Pin	14	14	14	14	14	14	14	14
Package Type	D	DGV	DGV	D	NS	PW	PW	PW
Industry STD Term	SOIC	TVSOP	TVSOP	SOIC	SOP	TSSOP	TSSOP	TSSOP
JEDEC Code	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G
Package QTY	50	2000	2000	2500	2000	2000	2000	2000
Carrier	TUBE	LARGE T&R	LARGE T&R	LARGE T&R	LARGE T&R	LARGE T&R	LARGE T&R	LARGE T&R
Device Marking	ALVC126	VA126	VA126	ALVC126	ALVC126	VA126	VA126	VA126
Width (mm)	3.91	4.4	4.4	3.91	5.3	4.4	4.4	4.4
Length (mm)	8.65	3.6	3.6	8.65	10.3	5	5	5
Thickness (mm)	1.58	1.05	1.05	1.58	1.95	1	1	1
Pitch (mm)	1.27	.4	.4	1.27	1.27	.65	.65	.65
Max Height (mm)	1.75	1.2	1.2	1.75	2	1.2	1.2	1.2
Mechanical Data	Herunterladen	Herunterladen	Herunterladen	Herunterladen	Herunterladen	Herunterladen	Herunterladen	Herunterladen

Parameter

Parameters / Models	SN74ALVC126D	SN74ALVC126DGVR	SN74ALVC126DGVRE4	SN74ALVC126DR	SN74ALVC126NSR	SN74ALVC126PWR	SN74ALVC126PWRE4	SN74ALVC126PWRG4
Bits	4	4	4	4	4	4	4	4
F @ Nom Voltage(Max), Mhz	100	100	100	100	100	100	100	100
ICC @ Nom Voltage(Max), mA	0.01	0.01	0.01	0.01	0.01	0.01	0.01	0.01
Operating Temperature Range, C	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85
Output Drive (IOL/IOH)(Max), mA	-24/24	-24/24	-24/24	-24/24	-24/24	-24/24	-24/24	-24/24
Package Group	SOIC	TVSOP	TVSOP	SOIC	SO	TSSOP	TSSOP	TSSOP
Package Size: mm2:W x L, PKG	14SOIC: 52 mm2: 6 x 8.65(SOIC)	14TVSOP: 23 mm2: 6.4 x 3.6(TVSOP)	14TVSOP: 23 mm2: 6.4 x 3.6(TVSOP)	14SOIC: 52 mm2: 6 x 8.65(SOIC)	14SO: 80 mm2: 7.8 x 10.2(SO)	14TSSOP: 32 mm2: 6.4 x 5(TSSOP)	14TSSOP: 32 mm2: 6.4 x 5(TSSOP)	14TSSOP: 32 mm2: 6.4 x 5(TSSOP)
Rating	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog
Schmitt Trigger	No	No	No	No	No	No	No	No
Technology Family	ALVC	ALVC	ALVC	ALVC	ALVC	ALVC	ALVC	ALVC
VCC(Max), V	3.6	3.6	3.6	3.6	3.6	3.6	3.6	3.6
VCC(Min), V	1.65	1.65	1.65	1.65	1.65	1.65	1.65	1.65
Voltage(Nom), V	1.8,2.5,2.7,3.3	1.8,2.5,2.7,3.3	1.8,2.5,2.7,3.3	1.8,2.5,2.7,3.3	1.8,2.5,2.7,3.3	1.8,2.5,2.7,3.3	1.8,2.5,2.7,3.3	1.8,2.5,2.7,3.3
tpd @ Nom Voltage(Max), ns	5.6,3.4,3.1	5.6,3.4,3.1	5.6,3.4,3.1	5.6,3.4,3.1	5.6,3.4,3.1	5.6,3.4,3.1	5.6,3.4,3.1	5.6,3.4,3.1

Öko-Plan

	SN74ALVC126D	SN74ALVC126DGVR	SN74ALVC126DGVRE4	SN74ALVC126DR	SN74ALVC126NSR	SN74ALVC126PWR	SN74ALVC126PWRE4	SN74ALVC126PWRG4
RoHS	Compliant	Compliant	Compliant	Compliant	Compliant	Compliant	Compliant	Compliant

Anwendungshinweise

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TI SN74ALVC16835 Component Specification Analysis for PC100
PDF, 43 Kb, Datei veröffentlicht: Aug 3, 1998
The PC100 standard establishes design parameters for the PC SDRAM DIMM that is designed to operate at 100 MHz. The 168-pin, 8-byte, registered SDRAM DIMM is a JEDEC-defined device (JC-42.5-96-146A). Some of the defined signal paths include data signals, address signals, and control signals. This application report discusses the SN74ALVC16835 18-bit universal bus driver that is available from T
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Logic Solutions for PC-100 SDRAM Registered DIMMs (Rev. A)
PDF, 96 Kb, Revision: A, Datei veröffentlicht: May 13, 1998
Design of high-performance personal computer (PC) systems that are capable of meeting the needs imposed by modern operating systems and software includes the use of large banks of SDRAMs on DIMMs (see Figure 1).To meet the demands of stable functionality over the broad spectrum of operating environments, meet system timing needs, and to support data integrity, the loads presented by the large
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16-Bit Widebus Logic Families in 56-Ball 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)
PDF, 895 Kb, Revision: B, Datei veröffentlicht: May 22, 2002
TI?s 56-ball MicroStar Jr.E package registered under JEDEC MO-225 has demonstrated through modeling and experimentation that it is an optimal solution for reducing inductance and capacitance improving thermal performance and minimizing board area usage in integrated bus functions. Multiple functions released in the 56-ball MicroStar Jr.E package have superior performance characteristics compa
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Understanding Advanced Bus-Interface Products Design Guide
PDF, 253 Kb, Datei veröffentlicht: May 1, 1996
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Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A)
PDF, 154 Kb, Revision: A, Datei veröffentlicht: Sep 8, 1999
In the last few years the trend toward reducing supply voltage (VCC) has continued as reflected in an additional specification of 2.5-V VCC for the AVC ALVT ALVC LVC LV and the CBTLV families.In this application report the different logic levels at VCC of 5 V 3.3 V 2.5 V and 1.8 V are compared. Within the report the possibilities for migration from 5-V logic and 3.3-V logic families

Modellreihe

Serie: SN74ALVC126 (8)

SN74ALVC126D SN74ALVC126DGVR SN74ALVC126DGVRE4 SN74ALVC126DR SN74ALVC126NSR SN74ALVC126PWR SN74ALVC126PWRE4 SN74ALVC126PWRG4

Herstellerklassifikation

Semiconductors> Logic> Buffer/Driver/Transceiver> Non-Inverting Buffer/Driver