Datasheet Texas Instruments SN65LVDS32PWG4 — Datenblatt

HerstellerTexas Instruments
SerieSN65LVDS32
ArtikelnummerSN65LVDS32PWG4
Datasheet Texas Instruments SN65LVDS32PWG4

Quad LVDS Empfänger 16-TSSOP -40 bis 85

Datenblätter

SNx5LVDS32, SN65LVDS3486, SN65LVDS9637 High-Speed Differential Line Receivers datasheet
PDF, 1.9 Mb, Revision: R, Datei veröffentlicht: Aug 6, 2014
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Preise

Status

Lifecycle StatusActive (Recommended for new designs)
Manufacture's Sample AvailabilityNo

Verpackung

Pin16
Package TypePW
Industry STD TermTSSOP
JEDEC CodeR-PDSO-G
Width (mm)4.4
Length (mm)5
Thickness (mm)1
Pitch (mm).65
Max Height (mm)1.2
Mechanical DataHerunterladen

Parameter

Approx. Price (US$)1.35 | 1ku
ESD HBM(kV)8
FunctionReceiver
ICC(Max)(mA)18
Input SignalLVDS
No. of Rx4
Operating Temperature Range(C)-40 to 85
Output SignalLVTTL
Package GroupTSSOP
Package Size: mm2:W x L (PKG)16TSSOP: 32 mm2: 6.4 x 5(TSSOP)
RatingCatalog
Signaling Rate(Mbps)100

Öko-Plan

RoHSNot Compliant
Pb FreeNo

Design Kits und Evaluierungsmodule

  • Evaluation Modules & Boards: SN65LVDS31-32EVM
    SN65LVDS31-32EVM Evaluation Module for LVDS31 and LVDS32
    Lifecycle Status: Active (Recommended for new designs)

Anwendungshinweise

  • Performance of LVDS with Different Cables (Rev. B)
    PDF, 246 Kb, Revision: B, Datei veröffentlicht: Feb 11, 2002
    This application report focuses on cable for use with LVDS devices rather than printed-circuit board interconnections. After a brief introduction to LVDS, the signal quality of seven different cables is evaluated using eye pattern measurements and TI's LVDS evaluation modules (EVMs). Since data transmission cable covers a wide range of cost and performance, this paper provides guidance for cable s
  • LVDS Multidrop Connections (Rev. A)
    PDF, 809 Kb, Revision: A, Datei veröffentlicht: Feb 11, 2002
    This application report describes design considerations for low-voltage differential swing (LVDS) multidrop connections. The report describes the maximum number of receivers possible versus signaling rate, signal quality, line length, output jitter, and common-mode voltage range when multidrop testing on a single LVDS line driver transmitting to numerous daisy-chained LVDS receivers.The LVDS rec

Modellreihe

Herstellerklassifikation

  • Semiconductors > Interface > LVDS/M-LVDS/ECL/CML > LVDS PHY (<800Mbps)