Datasheet Texas Instruments SN65LVDS105 — Datenblatt
| Hersteller | Texas Instruments |
| Serie | SN65LVDS105 |
1 LVTTL: 4 LVDS Clock Fanout Buffer
Datenblätter
SN65LVDS10x 4-Port LVDS and 4-Port TTL-to-LVDS Repeaters datasheet
PDF, 1.2 Mb, Revision: G, Datei veröffentlicht: Dec 31, 2015
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Preise
Status
| SN65LVDS105D | SN65LVDS105DG4 | SN65LVDS105DR | SN65LVDS105PW | SN65LVDS105PWG4 | SN65LVDS105PWR | SN65LVDS105PWRG4 | |
|---|---|---|---|---|---|---|---|
| Lifecycle Status | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) |
| Manufacture's Sample Availability | Yes | No | Yes | No | Yes | Yes | No |
Verpackung
| SN65LVDS105D | SN65LVDS105DG4 | SN65LVDS105DR | SN65LVDS105PW | SN65LVDS105PWG4 | SN65LVDS105PWR | SN65LVDS105PWRG4 | |
|---|---|---|---|---|---|---|---|
| N | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
| Pin | 16 | 16 | 16 | 16 | 16 | 16 | 16 |
| Package Type | D | D | D | PW | PW | PW | PW |
| Industry STD Term | SOIC | SOIC | SOIC | TSSOP | TSSOP | TSSOP | TSSOP |
| JEDEC Code | R-PDSO-G | R-PDSO-G | R-PDSO-G | R-PDSO-G | R-PDSO-G | R-PDSO-G | R-PDSO-G |
| Package QTY | 40 | 40 | 2500 | 90 | 90 | 2000 | 2000 |
| Carrier | TUBE | TUBE | LARGE T&R | TUBE | TUBE | LARGE T&R | LARGE T&R |
| Device Marking | LVDS105 | LVDS105 | LVDS105 | LVDS105 | LVDS105 | LVDS105 | LVDS105 |
| Width (mm) | 3.91 | 3.91 | 3.91 | 4.4 | 4.4 | 4.4 | 4.4 |
| Length (mm) | 9.9 | 9.9 | 9.9 | 5 | 5 | 5 | 5 |
| Thickness (mm) | 1.58 | 1.58 | 1.58 | 1 | 1 | 1 | 1 |
| Pitch (mm) | 1.27 | 1.27 | 1.27 | .65 | .65 | .65 | .65 |
| Max Height (mm) | 1.75 | 1.75 | 1.75 | 1.2 | 1.2 | 1.2 | 1.2 |
| Mechanical Data | Herunterladen | Herunterladen | Herunterladen | Herunterladen | Herunterladen | Herunterladen | Herunterladen |
Parameter
| Parameters / Models | SN65LVDS105D | SN65LVDS105DG4 | SN65LVDS105DR | SN65LVDS105PW | SN65LVDS105PWG4 | SN65LVDS105PWR | SN65LVDS105PWRG4 |
|---|---|---|---|---|---|---|---|
| Input Frequency(Max), MHz | 400 | 400 | 400 | 400 | 400 | 400 | 400 |
| Input Level | LVTTL | LVTTL | LVTTL | LVTTL | LVTTL | LVTTL | LVTTL |
| Number of Outputs | 4 | 4 | 4 | 4 | 4 | 4 | 4 |
| Operating Temperature Range, C | -40 to 85 | -40 to 85 | -40 to 85 | -40 to 85 | -40 to 85 | -40 to 85 | -40 to 85 |
| Output Frequency(Max), MHz | 400 | 400 | 400 | 400 | 400 | 400 | 400 |
| Output Level | LVDS | LVDS | LVDS | LVDS | LVDS | LVDS | LVDS |
| Package Group | SOIC | SOIC | SOIC | TSSOP | TSSOP | TSSOP | TSSOP |
| Package Size: mm2:W x L, PKG | 16SOIC: 59 mm2: 6 x 9.9(SOIC) | 16SOIC: 59 mm2: 6 x 9.9(SOIC) | 16SOIC: 59 mm2: 6 x 9.9(SOIC) | 16TSSOP: 32 mm2: 6.4 x 5(TSSOP) | 16TSSOP: 32 mm2: 6.4 x 5(TSSOP) | 16TSSOP: 32 mm2: 6.4 x 5(TSSOP) | 16TSSOP: 32 mm2: 6.4 x 5(TSSOP) |
| Rating | Catalog | Catalog | Catalog | Catalog | Catalog | Catalog | Catalog |
| VCC, V | 3.3 | 3.3 | 3.3 | 3.3 | 3.3 | 3.3 | 3.3 |
| VCC Out, V | 3.3 | 3.3 | 3.3 | 3.3 | 3.3 | 3.3 | 3.3 |
Öko-Plan
| SN65LVDS105D | SN65LVDS105DG4 | SN65LVDS105DR | SN65LVDS105PW | SN65LVDS105PWG4 | SN65LVDS105PWR | SN65LVDS105PWRG4 | |
|---|---|---|---|---|---|---|---|
| RoHS | Compliant | Compliant | Compliant | Compliant | Compliant | Compliant | Compliant |
Modellreihe
Serie: SN65LVDS105 (7)
Herstellerklassifikation
- Semiconductors> Clock and Timing> Clock Buffers> Differential