Datasheet Texas Instruments SN54LVTH573 — Datenblatt

HerstellerTexas Instruments
SerieSN54LVTH573
Datasheet Texas Instruments SN54LVTH573

3.3-V ABT Octal Transparente D-Latches mit 3-Zustands-Ausgängen

Datenblätter

SN54LVTH573, SN74LVTH573 datasheet
PDF, 1.5 Mb, Revision: H, Datei veröffentlicht: Sep 15, 2003
Auszug aus dem Dokument

Preise

Status

5962-9583101Q2A5962-9583101QRA5962-9583101QSASNJ54LVTH573FKSNJ54LVTH573JSNJ54LVTH573W
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityNoNoNoNoNoNo

Verpackung

5962-9583101Q2A5962-9583101QRA5962-9583101QSASNJ54LVTH573FKSNJ54LVTH573JSNJ54LVTH573W
N123456
Pin202020202020
Package TypeFKJWFKJW
Industry STD TermLCCCCDIPCFPLCCCCDIPCFP
JEDEC CodeS-CQCC-NR-GDIP-TR-GDFP-FS-CQCC-NR-GDIP-TR-GDFP-F
Package QTY111111
CarrierTUBETUBETUBETUBETUBETUBE
Device Marking5962-ASNJ54LVTH573WSNJ54LVTHSNJ54LVTH573JA
Width (mm)8.896.926.928.896.926.92
Length (mm)8.8924.213.098.8924.213.09
Thickness (mm)1.834.571.841.834.571.84
Pitch (mm)1.272.541.271.272.541.27
Max Height (mm)2.035.082.452.035.082.45
Mechanical DataHerunterladenHerunterladenHerunterladenHerunterladenHerunterladenHerunterladen

Parameter

Parameters / Models5962-9583101Q2A
5962-9583101Q2A
5962-9583101QRA
5962-9583101QRA
5962-9583101QSA
5962-9583101QSA
SNJ54LVTH573FK
SNJ54LVTH573FK
SNJ54LVTH573J
SNJ54LVTH573J
SNJ54LVTH573W
SNJ54LVTH573W
3-State OutputYesYesYesYesYesYes
Bits888888
F @ Nom Voltage(Max), Mhz160160160160160160
ICC @ Nom Voltage(Max), mA555555
Input TypeTTLTTLTTLTTLTTLTTL
Operating Temperature Range, C-55 to 125-55 to 125-55 to 125-55 to 125-55 to 125-55 to 125
Output Drive (IOL/IOH)(Max), mA48/-2448/-2448/-2448/-2448/-2448/-24
Output TypeTTLTTLTTLTTLTTLTTL
Package GroupLCCCCDIPCFPLCCCCDIPCFP
Package Size: mm2:W x L, PKG20LCCC: 79 mm2: 8.89 x 8.89(LCCC)See datasheet (CDIP)See datasheet (CFP)20LCCC: 79 mm2: 8.89 x 8.89(LCCC)See datasheet (CDIP)See datasheet (CFP)
RatingMilitaryMilitaryMilitaryMilitaryMilitaryMilitary
Technology FamilyLVTLVTLVTLVTLVTLVT
VCC(Max), V3.63.63.63.63.63.6
VCC(Min), V2.72.72.72.72.72.7
tpd @ Nom Voltage(Max), ns4.54.54.54.54.54.5

Öko-Plan

5962-9583101Q2A5962-9583101QRA5962-9583101QSASNJ54LVTH573FKSNJ54LVTH573JSNJ54LVTH573W
RoHSSee ti.comSee ti.comSee ti.comSee ti.comSee ti.comSee ti.com

Anwendungshinweise

  • Input and Output Characteristics of Digital Integrated Circuits
    PDF, 1.7 Mb, Datei veröffentlicht: Oct 1, 1996
    This report contains a comprehensive collection of the input and output characteristic curves of typical integrated circuits from various logic families. These curves go beyond the information given in data sheets by providing additional details regarding the characteristics of the components. This knowledge is particularly useful when for example a decision must be made as to which circuit shou
  • LVT Family Characteristics (Rev. A)
    PDF, 98 Kb, Revision: A, Datei veröffentlicht: Mar 1, 1998
    To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti
  • LVT-to-LVTH Conversion
    PDF, 84 Kb, Datei veröffentlicht: Dec 8, 1998
    Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.
  • Understanding Advanced Bus-Interface Products Design Guide
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  • Power-Up Behavior of Clocked Devices (Rev. A)
    PDF, 34 Kb, Revision: A, Datei veröffentlicht: Feb 6, 2015
  • TI IBIS File Creation Validation and Distribution Processes
    PDF, 380 Kb, Datei veröffentlicht: Aug 29, 2002
    The Input/Output Buffer Information Specification (IBIS) also known as ANSI/EIA-656 has become widely accepted among electronic design automation (EDA) vendors semiconductor vendors and system designers as the format for digital electrical interface data. Because IBIS models do not reveal proprietary internal processes or architectural information semiconductor vendors? support for IBIS con
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    PDF, 150 Kb, Datei veröffentlicht: Oct 1, 1996
    Many applications require the ability to exchange modules in electronic systems without removing the supply voltage from the module (live insertion). For example an electronic telephone exchange must always remain operational even during module maintenance and repair. To avoid damaging components additional circuitry modifications are necessary. This document describes in detail the phenomena tha
  • Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices
    PDF, 209 Kb, Datei veröffentlicht: May 10, 2002
    Many telecom and networking applications require that cards be inserted and extracted from a live backplane without interrupting data or damaging components. To achieve this interface terminals of the card must be electrically isolated from the bus system during insertion or extraction from the backplane. To facilitate this Texas Instruments provides bus-interface and logic devices with features
  • Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)
    PDF, 105 Kb, Revision: A, Datei veröffentlicht: Aug 1, 1997
    The spectrum of bus-interface devices with damping resistors or balanced/light output drive currently offered by various logic vendors is confusing at best. Inconsistencies in naming conventions and methods used for implementation make it difficult to identify the best solution for a given application. This report attempts to clarify the issue by looking at several vendors? approaches and discussi
  • Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)
    PDF, 614 Kb, Revision: C, Datei veröffentlicht: Dec 2, 2015
  • Semiconductor Packing Material Electrostatic Discharge (ESD) Protection
    PDF, 337 Kb, Datei veröffentlicht: Jul 8, 2004
    Forty-eight-pin TSSOP components that were packaged using Texas Instruments (TI) standard packing methodology were subjected to electrical discharges between 0.5 and 20 kV as generated by an IEC ESD simulator to determine the level of ISD protection provided by the packing materials. The testing included trays tape and reel and magazines. Additional units were subjected to the same discharge
  • 16-Bit Widebus Logic Families in 56-Ball 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)
    PDF, 895 Kb, Revision: B, Datei veröffentlicht: May 22, 2002
    TI?s 56-ball MicroStar Jr.E package registered under JEDEC MO-225 has demonstrated through modeling and experimentation that it is an optimal solution for reducing inductance and capacitance improving thermal performance and minimizing board area usage in integrated bus functions. Multiple functions released in the 56-ball MicroStar Jr.E package have superior performance characteristics compa
  • Introduction to Logic
    PDF, 93 Kb, Datei veröffentlicht: Apr 30, 2015
  • Implications of Slow or Floating CMOS Inputs (Rev. D)
    PDF, 260 Kb, Revision: D, Datei veröffentlicht: Jun 23, 2016

Modellreihe

Herstellerklassifikation

  • Semiconductors> Space & High Reliability> Logic Products> Flip-Flop/Latch/Registers