Datasheet Texas Instruments DS99R101 — Datenblatt

HerstellerTexas Instruments
SerieDS99R101
Datasheet Texas Instruments DS99R101

DC-symmetrischer 24-Bit-LVDS-Serializer mit 3-40 MHz

Datenblätter

DS99R101/DS99R102 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer datasheet
PDF, 909 Kb, Revision: D, Datei veröffentlicht: Apr 16, 2013
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Preise

Status

DS99R101VS/NOPBDS99R101VSX/NOPB
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityNoYes

Verpackung

DS99R101VS/NOPBDS99R101VSX/NOPB
N12
Pin4848
Package TypePFBPFB
Industry STD TermTQFPTQFP
JEDEC CodeS-PQFP-GS-PQFP-G
Package QTY2501000
CarrierJEDEC TRAY (10+1)LARGE T&R
Device MarkingDS99R101VS
Width (mm)77
Length (mm)77
Thickness (mm)11
Pitch (mm).5.5
Max Height (mm)1.21.2
Mechanical DataHerunterladenHerunterladen

Parameter

Parameters / ModelsDS99R101VS/NOPB
DS99R101VS/NOPB
DS99R101VSX/NOPB
DS99R101VSX/NOPB
Approx. Price (US$)4.51 | 1ku
Color Depth, bpp18
Color Depth(bpp)18
Diagnostics--
EMI ReductionProgressive Turn On (PTO)Progressive Turn On (PTO)
FunctionSerializerSerializer
Input CompatibilityLVCMOSLVCMOS
Operating Temperature Range, C0 to 70
Operating Temperature Range(C)0 to 70
Output CompatibilityFPD-Link LVDSFPD-Link LVDS
Package GroupTQFPTQFP
Package Size: mm2:W x L, PKG48TQFP: 81 mm2: 9 x 9(TQFP)
Package Size: mm2:W x L (PKG)48TQFP: 81 mm2: 9 x 9(TQFP)
Pixel Clock Min, MHz3
Pixel Clock Min(MHz)3
Pixel Clock(Max), MHz40
Pixel Clock(Max)(MHz)40
RatingCatalogCatalog
Signal Conditioning--
Special Features--
SupplyVoltage(Volt)3.3
Total Throughput, Mbps960
Total Throughput(Mbps)960

Öko-Plan

DS99R101VS/NOPBDS99R101VSX/NOPB
RoHSCompliantCompliant
Pb FreeYes

Anwendungshinweise

  • LVDS Repeaters and Crosspoints Extend the Reach of FPD-Link II Interfaces (Rev. A)
    PDF, 101 Kb, Revision: A, Datei veröffentlicht: Apr 29, 2013
    This application note introduces Texas Instrument’s LVDS devices with built-in pre-emphasis andequalization circuits, recommends when it makes sense to employ them with the FPD-Link II SER/DES,shows how to optimally interface them to the SER/DES, and discusses distance gains that may berealized with their signal enhancing functions.
  • Extending the Reach of a FPD-Link II Interface with Cable Drivers and Equalizers (Rev. A)
    PDF, 118 Kb, Revision: A, Datei veröffentlicht: Apr 26, 2013
    TI's family of embedded clock LVDS SER/DES (FPD-link II) provides a 2-wire serial interface for displayapplications up to distances of 10 meters.

Modellreihe

Herstellerklassifikation

  • Semiconductors> Interface> Display & Imaging SerDes> FPD-Link II SerDes