Datasheet Texas Instruments DS92LV1224 — Datenblatt
| Hersteller | Texas Instruments |
| Serie | DS92LV1224 |
10-Bit-Deserializer mit 30-66 MHz
Datenblätter
DS92LV1224 30-66 MHz 10 Bit Bus LVDS Deserializer datasheet
PDF, 1.2 Mb, Revision: A, Datei veröffentlicht: Apr 16, 2013
Auszug aus dem Dokument
Preise
Status
| DS92LV1224TMSA | DS92LV1224TMSA/NOPB | DS92LV1224TMSAX/NOPB | |
|---|---|---|---|
| Lifecycle Status | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) |
| Manufacture's Sample Availability | Yes | No | No |
Verpackung
| DS92LV1224TMSA | DS92LV1224TMSA/NOPB | DS92LV1224TMSAX/NOPB | |
|---|---|---|---|
| N | 1 | 2 | 3 |
| Pin | 28 | 28 | 28 |
| Package Type | DB | DB | DB |
| Industry STD Term | SSOP | SSOP | SSOP |
| JEDEC Code | R-PDSO-G | R-PDSO-G | R-PDSO-G |
| Package QTY | 47 | 47 | 2000 |
| Carrier | TUBE | TUBE | LARGE T&R |
| Device Marking | MSA | MSA | DS92LV1224T |
| Width (mm) | 5.3 | 5.3 | 5.3 |
| Length (mm) | 10.2 | 10.2 | 10.2 |
| Thickness (mm) | 1.95 | 1.95 | 1.95 |
| Pitch (mm) | .65 | .65 | .65 |
| Max Height (mm) | 2 | 2 | 2 |
| Mechanical Data | Herunterladen | Herunterladen | Herunterladen |
Parameter
| Parameters / Models | DS92LV1224TMSA | DS92LV1224TMSA/NOPB | DS92LV1224TMSAX/NOPB |
|---|---|---|---|
| ESD, kV | 2 | 2 | 2 |
| Function | Deserializer | Deserializer | Deserializer |
| Input Compatibility | LVDS,BLVDS | LVDS,BLVDS | LVDS,BLVDS |
| Operating Temperature Range, C | -40 to 85 | -40 to 85 | -40 to 85 |
| Output Compatibility | LVTTL | LVTTL | LVTTL |
| Package Group | SSOP | SSOP | SSOP |
| Package Size: mm2:W x L, PKG | 28SSOP: 80 mm2: 7.8 x 10.2(SSOP) | 28SSOP: 80 mm2: 7.8 x 10.2(SSOP) | 28SSOP: 80 mm2: 7.8 x 10.2(SSOP) |
| Protocols | Channel-Link I | Channel-Link I | Channel-Link I |
| Rating | Catalog | Catalog | Catalog |
| Supply Voltage(s), V | 3.3 | 3.3 | 3.3 |
Öko-Plan
| DS92LV1224TMSA | DS92LV1224TMSA/NOPB | DS92LV1224TMSAX/NOPB | |
|---|---|---|---|
| RoHS | See ti.com | Compliant | Compliant |
Anwendungshinweise
- How to Validate BLVDS SER/DES Signal Integrity Using an Eye Mask (Rev. A)PDF, 2.0 Mb, Revision: A, Datei veröffentlicht: Apr 26, 2013
The following application report contains information that will help you validate signal quality on a BLVDS SER/DES link. How to capture an eye pattern, how to generate an eye mask, and how to validate signal quality are all explained in detail in this document. - DS15BA101 & DS15EA101 Enable Long Reach Applications for Embedded Clock SER/DES (Rev. E)PDF, 170 Kb, Revision: E, Datei veröffentlicht: Apr 29, 2013
Reduction in system size, increase in system performance and savings in system cost are valuablebenefits that SER/DES devices (Serializers and Deserializers) bring to many system designers. Thesebenefits are the reason why SER/DES are integral pieces of many of today’s high-speed systems.One of the design constraints for these systems is the maximum transmission distance between a serializer
Modellreihe
Serie: DS92LV1224 (3)
Herstellerklassifikation
- Semiconductors> Interface> Serializer, Deserializer> BLVDS/LVDS SerDes (<100 MHz)