Datasheet Texas Instruments DS90CR215 — Datenblatt

HerstellerTexas Instruments
SerieDS90CR215
Datasheet Texas Instruments DS90CR215

+ 3,3 V Daten-Strobe-LVDS-21-Bit-Kanalverbindung mit steigender Flanke - 66 MHz

Datenblätter

DS90CR215/216 3.3V Rising Edge Data Strobe LVDS 21Bit Chanlnk - 66MHz datasheet
PDF, 1.1 Mb, Revision: D, Datei veröffentlicht: Apr 17, 2013
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Preise

Status

DS90CR215MTDDS90CR215MTD/NOPBDS90CR215MTDX/NOPB
Lifecycle StatusNRND (Not recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityYesNoNo

Verpackung

DS90CR215MTDDS90CR215MTD/NOPBDS90CR215MTDX/NOPB
N123
Pin484848
Package TypeDGGDGGDGG
Industry STD TermTSSOPTSSOPTSSOP
JEDEC CodeR-PDSO-GR-PDSO-GR-PDSO-G
Package QTY38381000
CarrierTUBETUBELARGE T&R
Device Marking>BDS90CR215MTD>B
Width (mm)6.16.16.1
Length (mm)12.512.512.5
Thickness (mm)1.151.151.15
Pitch (mm).5.5.5
Max Height (mm)1.21.21.2
Mechanical DataHerunterladenHerunterladenHerunterladen

Parameter

Parameters / ModelsDS90CR215MTD
DS90CR215MTD
DS90CR215MTD/NOPB
DS90CR215MTD/NOPB
DS90CR215MTDX/NOPB
DS90CR215MTDX/NOPB
Clock Max, MHz666666
Clock Min, MHz202020
Compression Ratio21 to 321 to 321 to 3
Data Throughput, Mbps138613861386
ESD, kV777
FunctionSerializerSerializerSerializer
Input CompatibilityLVCMOSLVCMOSLVCMOS
Operating Temperature Range, C-40 to 85-40 to 85-40 to 85
Output CompatibilityLVDSLVDSLVDS
Package GroupTSSOPTSSOPTSSOP
Package Size: mm2:W x L, PKG48TSSOP: 101 mm2: 8.1 x 12.5(TSSOP)48TSSOP: 101 mm2: 8.1 x 12.5(TSSOP)48TSSOP: 101 mm2: 8.1 x 12.5(TSSOP)
Parallel Bus Width, bits212121
ProtocolsChannel-Link IChannel-Link IChannel-Link I
RatingCatalogCatalogCatalog
Supply Voltage(s), V3.33.33.3

Öko-Plan

DS90CR215MTDDS90CR215MTD/NOPBDS90CR215MTDX/NOPB
RoHSSee ti.comCompliantCompliant

Anwendungshinweise

  • CHANNEL LINK Moving and Shaping Information In Point-To-Point Applications
    PDF, 269 Kb, Datei veröffentlicht: Oct 5, 1998
  • Multi-Drop Channel-Link Operation
    PDF, 212 Kb, Datei veröffentlicht: Oct 4, 2004
  • Receiver Skew Margin for Channel Link I and FPD Link I Devices
    PDF, 418 Kb, Datei veröffentlicht: Jan 13, 2016
  • AN-1108 Channel-Link PCB and Interconnect Design-In Guidelines
    PDF, 245 Kb, Datei veröffentlicht: May 15, 2004
    Application Note 1108 Channel-Link PCB and Interconnect Design-In Guidelines

Modellreihe

Herstellerklassifikation

  • Semiconductors> Interface> Serializer, Deserializer> Channel Link I