Datasheet Texas Instruments DS90C124IVSX/NOPB — Datenblatt

5-35 MHz DC-symmetrischer 24-Bit-FPD-Link II-Deserializer 48-TQFP -40 bis 105

Datenblätter

PDF, 2.1 Mb, Revision: M, Datei veröffentlicht: Jan 3, 2017

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Lifecycle Status	Active (Recommended for new designs)
Manufacture's Sample Availability	No

Color Depth	18 bpp
Diagnostics	BIST
EMI Reduction	Progressive Turn On (PTO),Slew Rate Control
Function	Deserializer
Input Compatibility	FPD-Link II LVDS
Operating Temperature Range	-40 to 105 C
Output Compatibility	LVCMOS
Package Group	TQFP
Package Size: mm2:W x L	48TQFP: 81 mm2: 9 x 9(TQFP) PKG
Pixel Clock Min	5 MHz
Pixel Clock(Max)	35 MHz
Rating	Catalog
Signal Conditioning	-
Special Features	-
Total Throughput	840 Mbps

RoHS

Compliant

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PDF, 101 Kb, Revision: A, Datei veröffentlicht: Apr 29, 2013
This application note introduces Texas InstrumentвЂ™s LVDS devices with built-in pre-emphasis andequalization circuits, recommends when it makes sense to employ them with the FPD-Link II SER/DES,shows how to optimally interface them to the SER/DES, and discusses distance gains that may berealized with their signal enhancing functions.
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Extending the Reach of a FPD-Link II Interface with Cable Drivers and Equalizers (Rev. A)
PDF, 118 Kb, Revision: A, Datei veröffentlicht: Apr 26, 2013
TI's family of embedded clock LVDS SER/DES (FPD-link II) provides a 2-wire serial interface for displayapplications up to distances of 10 meters.

Serie: DS90C124 (2)