Datasheet Texas Instruments DS32EL0124SQX/NOPB — Datenblatt

125 MHz - 312,5 MHz FPGA-Link-Deserializer mit paralleler DDR-LVDS-Schnittstelle 48-WQFN -40 bis 85

Datenblätter

PDF, 2.6 Mb, Revision: K, Datei veröffentlicht: Apr 15, 2013

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Lifecycle Status	Active (Recommended for new designs)
Manufacture's Sample Availability	No

Operating Temperature Range	-40 to 85 C
Package Group	WQFN
Package Size: mm2:W x L	48WQFN: 49 mm2: 7 x 7(WQFN) PKG
Rating	Catalog

RoHS

Compliant

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Expanding the Payload w/FPGA-Link DS32ELX0421 and DS32ELX0124 SER/DES (Rev. A)
PDF, 60 Kb, Revision: A, Datei veröffentlicht: Apr 26, 2013
High data payload, reaching across 10вЂ™s of meters of low cost media, is stretching the current boundariesof high speed transceiver solutions.Whether the data is packetized for fiber channel at 4.25 Gbps or twostreams of HD video content are multiplexed in a single link, more markets are emerging to push the limitsof current high speed data solutions.
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LVDS Timing DS32ELX0421 and DS32ELX0124 Serializers and Deserializers (Rev. A)
PDF, 55 Kb, Revision: A, Datei veröffentlicht: Apr 26, 2013
The highly integrated FPGA-Link SerDes chipset (DS32ELX0421 and DS32ELX0124) enables low-costFPGAs in a variety of high performance, high-speed applications. They feature advanced on-chip signaland clock conditioning circuitry that extends the data transmission reach of CAT-6 (shielded 24 AWG)cable beyond 20 meters without additional external components.

Serie: DS32EL0124 (3)