Datasheet Texas Instruments DS25BR110 — Datenblatt

HerstellerTexas Instruments
SerieDS25BR110
Datasheet Texas Instruments DS25BR110

3.125 Gbit / s LVDS-Puffer mit Empfangsausgleich

Datenblätter

DS25BR110 3.125 Gbps LVDS Buffer with Receive Equalization datasheet
PDF, 879 Kb, Revision: E, Datei veröffentlicht: Apr 14, 2013
Auszug aus dem Dokument

Preise

Status

DS25BR110TSD/NOPBDS25BR110TSDX/NOPB
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityNoYes

Verpackung

DS25BR110TSD/NOPBDS25BR110TSDX/NOPB
N12
Pin88
Package TypeNGQNGQ
Industry STD TermWSONWSON
JEDEC CodeS-PDSO-NS-PDSO-N
Package QTY10004500
CarrierSMALL T&RLARGE T&R
Device Marking2R1102R110
Width (mm)33
Length (mm)33
Thickness (mm).8.8
Pitch (mm).5.5
Max Height (mm).8.8
Mechanical DataHerunterladenHerunterladen

Parameter

Parameters / ModelsDS25BR110TSD/NOPB
DS25BR110TSD/NOPB
DS25BR110TSDX/NOPB
DS25BR110TSDX/NOPB
Device TypeBufferBuffer
ESD HBM, kV77
FunctionEqualizerEqualizer
ICC(Max), mA4343
Operating Temperature Range, C-40 to 85-40 to 85
Package GroupWSONWSON
Package Size: mm2:W x L, PKGSee datasheet (WSON)See datasheet (WSON)
ProtocolsLVDSLVDS

Öko-Plan

DS25BR110TSD/NOPBDS25BR110TSDX/NOPB
RoHSCompliantCompliant

Anwendungshinweise

  • Extending the Signal Path Over Data Trans Lines Using LVDS Signal Conditioning
    PDF, 575 Kb, Datei veröffentlicht: Aug 2, 2007
  • LVDS Repeaters and Crosspoints Extend the Reach of FPD-Link II Interfaces (Rev. A)
    PDF, 101 Kb, Revision: A, Datei veröffentlicht: Apr 29, 2013
    This application note introduces Texas Instrument’s LVDS devices with built-in pre-emphasis andequalization circuits, recommends when it makes sense to employ them with the FPD-Link II SER/DES,shows how to optimally interface them to the SER/DES, and discusses distance gains that may berealized with their signal enhancing functions.
  • AN-1957 LVDS Signal Conditioners Reduce Data-Dependent Jitter (Rev. A)
    PDF, 275 Kb, Revision: A, Datei veröffentlicht: Apr 26, 2013
    Jitter is a phenomenon troubling many designers of high-speed interfaces. It reduces available timingmargin, limits transmission distance between a transmitter and a receiver, and increases system cost bydemanding better performing and more expensive interconnects. LVDS interfaces are not spared fromthese ill effects as they now operate at bit rates exceeding the 3 Gbps mark. Texas Instrumen

Modellreihe

Herstellerklassifikation

  • Semiconductors> Interface> Signal Conditioners> Equalizer