Datasheet Texas Instruments DRA746BPGABCRQ1 — Datenblatt
Hersteller | Texas Instruments |
Serie | DRA746 |
Artikelnummer | DRA746BPGABCRQ1 |
Doppelter 1,5-GHz-Arm-Cortex-A15-SoC-Prozessor für Infotainment 760-FCBGA
Datenblätter
DRA75x, DRA74x Infotainment Applications Processor Silicon Revision 2.0 datasheet
PDF, 7.1 Mb, Revision: C, Datei veröffentlicht: Jun 6, 2017
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Preise
Status
Lifecycle Status | Preview (Device has been announced but is not in production. Samples may or may not be available) |
Manufacture's Sample Availability | No |
Verpackung
Pin | 760 |
Package Type | ABC |
Industry STD Term | FCBGA |
JEDEC Code | S-PBGA-N |
Package QTY | 250 |
Carrier | LARGE T&R |
Device Marking | DRA746BPGABCQ1 |
Width (mm) | 23 |
Length (mm) | 23 |
Thickness (mm) | 2.39 |
Pitch (mm) | .8 |
Max Height (mm) | 2.96 |
Mechanical Data | Herunterladen |
Parameter
ARM CPU | 2 ARM Cortex-A15 |
ARM MHz | 1500 Max. |
Co-Processor | 2 ARM Cortex-M4 s |
DSP | 1 C66x |
DSP MHz | 700 Max. |
Display Options | 1 HDMI OUT,3 LCD OUT |
EMAC | 10/100/1000,2-port 1Gb switch |
EMIF | 2 DDR2,2 DDR3,2 DDR3L |
Graphics Acceleration | 1 2D,2 3D |
Hardware Accelerators | 1 Image Video Accelerator,2 Viterbi Decoder,Audio Tracking |
MMC/SD | 1x SDIO 4b,1x SDIO 8b,1x UHSI 4b,1x eMMC 8b |
McASP | 8 |
Other On-Chip Memory | 512 KB |
PCIe | 1 PCIe Gen2 |
Serial I/O | CAN,I2C,SPI,UART,USB |
USB | 1 USB3.0,3 USB2.0 |
Video Input Ports | 6 |
Öko-Plan
RoHS | Compliant |
Design Kits und Evaluierungsmodule
- Evaluation Modules & Boards: J6EVM5777
Jacinto 6 Evaluation Module
Lifecycle Status: Active (Recommended for new designs)
Anwendungshinweise
- Software Guidelines to EMIF/DDR3 Configuration on DRA7xx DevicesPDF, 62 Kb, Datei veröffentlicht: Jul 12, 2017
This application report provides information on EMIF/DDR configuration on dra7xx devices and guidelines to changes to be made in SPL/U-boot source code. - DRA74x_75x/DRA72x PerformancePDF, 6.6 Mb, Datei veröffentlicht: Jun 17, 2016
This application report provides information on the DRA74x_75x and DRA72x device throughput performances and describes the DRA74x_75x and DRA72x System-on-Chip (SoC) architecture, data path infrastructure, and constraints that affect the throughput and different optimization techniques for optimum system performance. This document also provides information on the maximum possible throughput perfor - Linux Boot Time Optimizations on DRA7xx DevicesPDF, 197 Kb, Datei veröffentlicht: Mar 31, 2017
This application report provides information on benchmarking and optimizing u-boot and Linux kernel on DRA7xx platform. It also demonstrates how to reach the userspace in less than 3 seconds from reset using generic boot time optimizations. - Flashing Binaries to DRA7xx Factory Boards Using DFUPDF, 42 Kb, Datei veröffentlicht: Apr 14, 2016
This application report provides detailed procedures for flashing the binary images to eMMC Flash memory using Device Firmware Upgrade (DFU). Generally, the MMC/SD boot mode can be used to boot the fresh production board/EVM. In case there is not an external MMC/SD card available as part of production EVM or final product, this application report will be useful to flash the images to the factory b - Early Splash Screen on DRA7x DevicesPDF, 721 Kb, Datei veröffentlicht: Jan 31, 2017
This application report provides information on how to display a splash screen as soon as possible on the DRA7xx devices and perform a glitch-free transition from the splash screen to the full system UI. The steps in this document are demonstrated using U-Boot and Linux kernel. The same steps can be applied to other bootloaders and operating systems. - Interfacing DRA75x and DRA74x Audio to Analog Codecs (Rev. A)PDF, 57 Kb, Revision: A, Datei veröffentlicht: Feb 17, 2017
DRA7xx Infotainment Application Processor offers an audio solution based on the multichannel audio serial port (McASP). McASP is a very flexible interface capable of interfacing with audio devices using protocols like Inter-IC Sound (I2S), PCM, TDM, S/PDIF. DRA7xx audio solution at LinuxВ® kernel level uses ALSA System-on-Chip (ASoC) layer with independent drivers for the DMA engine, CPU-side audio - Tools and Techniques for Audio DebuggingPDF, 409 Kb, Datei veröffentlicht: Apr 13, 2016
Debugging audio issues can be a challenging task due to the dynamic nature of the audio systems, in terms of runtime routing flexibility, gain control, and so forth. Investigating the root cause of system level issues is a difficult task without the appropriate tools and techniques.This document discusses some of the available tools for debugging audio issues. These tools span from TI-speci - Gstreamer Migration GuidelinesPDF, 229 Kb, Datei veröffentlicht: Apr 26, 2016
Gstreamer is a widely used multimedia framework. It is supported by GLSDK. New versions of gstreamer come out every month with a lot of bug fixes. The examples and steps are based on Gst 0.10 to Gst 1.2 migration. Anyone who wants to adapt to a newer or older version can use this as a guideline.The steps for creating and building a recipe are based on the yocto setup. The migration steps ar - Android Boot Optimization for IVI SystemsPDF, 51 Kb, Datei veröffentlicht: Feb 29, 2016
Boot-time optimizations are a critical component for a better Auto infotainment experience. This application report captures the details on how to improve android boot time and is meant to be a reference implementation. The end user (OEM/ODM/Customer/Product Owner) can review the optimizations that were tried and make a choice for the final product accordingly. - Using Peripheral Boot and DFU for Rapid Development on Jacinto 6 DevicesPDF, 49 Kb, Datei veröffentlicht: Feb 15, 2017
This application report describes how to use peripheral boot and Device Firmware Upgrade (DFU) to reduce the time required to load updated binaries to various cores of a Jacinto 6 (DRA7xx) family device. - Debugging Tools and Techniques With IPC3.xPDF, 353 Kb, Datei veröffentlicht: Mar 30, 2016
There are several useful tools and techniques that enable you to debug issues encountered when using software that leverages IPC3.x. With some guidance on the tools and techniques, you can confidently debug the IPC and the remote core software.This application report guides the customers on the tools and techniques for debugging with IPC3.x - Modifying Memory Usage for IPUMM Applications Loaded IPC 3.x for DRA75x, DRA74x (Rev. A)PDF, 78 Kb, Revision: A, Datei veröffentlicht: Jan 15, 2016
The default Image Processing Unit (IPU) image for DRA7xx IPU provides numerous capabilities for a rich multimedia experience. However, not all customers will want to use all of the capabilities, or may wish to add new capabilities. If not all of the capabilities are used, then the memory usage can be reduced. Similarly, if new capabilities are added, the memory usage can be increased.This d - Jacinto6 Spread Spectrum Clocking ConfigurationPDF, 113 Kb, Datei veröffentlicht: Sep 1, 2015
- Using DSS Write-Back Pipeline for RGB-to-YUV Conversion on DRA7xx DevicesPDF, 90 Kb, Datei veröffentlicht: Aug 14, 2017
This application report provides information on how to use the DSS Write-back pipeline for RGB-to-YUV colorspace conversion on DRA7xx platform running Processor SDK Linux Automotive. - Quality of Service (QoS) Knobs for DRA74x, DRA75x & TDA2x Family of Devices (Rev. A)PDF, 148 Kb, Revision: A, Datei veröffentlicht: Dec 15, 2016
This application report lists various quality-of-service (QoS) knobs that are implemented in DRA74x, DRA75x and TDA2x system-on-chip (SoC) family of devices. These QoS knobs aid to optimize overall system performance while running several concurrent application scenarios. - Optimizing DRA7xx and TDA2xx Processors for use with Video Display SERDES (Rev. A)PDF, 132 Kb, Revision: A, Datei veröffentlicht: Jun 14, 2017
The purpose of this application report is to provide guidance on configuring DRA7xx and TDA2xx processors to meet video Serializer/Deserializer (SerDes) jitter requirements. - A Guide to Debugging With CCS on the DRA75x, DRA74x, TDA2x and TDA3x Family of D (Rev. A)PDF, 3.2 Mb, Revision: A, Datei veröffentlicht: Aug 19, 2016
Being able to look into the state of the device when an application fails to run as expected is a key enabler while debugging the application. This application report walks through the different steps required to setup the TI Code Composer Studioв„ў (CCS), as well as how to debug applications on the DRA7x, TDA2x and TDA3x family of devices. The document starts with describing basic CCS debugging tec - Guide to fix Perf Issues Using QoS Knobs for DRA74x, DRA75x, TDA2x & TD3x DevicePDF, 612 Kb, Datei veröffentlicht: Aug 13, 2014
This application report provides a methodology through which performance issues can be identified and fixed in systems using DRA74x, DRA75x, TDA2x and TDA3x family of devices. - ECC/EDC on TDAxx (Rev. A)PDF, 109 Kb, Revision: A, Datei veröffentlicht: Jul 5, 2017
TDA2x and TDA3x series of automotive processor are designed to be used in automotive safety systems. To enable safety, these processors come with error detection and correction (EDC) support for various memories. This application report provides an overview and usage description of EDC. - EMIF Tools (Rev. A)PDF, 207 Kb, Revision: A, Datei veröffentlicht: Jun 5, 2017
At the center of every application is the need for memory. With limited on-chip processor memory, external memory serves as a solution for large software systems and data storage, and an unstable external memory interface can result in system failures or hinder software development. To prevent potential system level anomalies and ensure robust systems, hardware must be configured correctly and tes
Modellreihe
Serie: DRA746 (3)
- DRA746APGABCQ1 DRA746BPGABCQ1 DRA746BPGABCRQ1
Herstellerklassifikation
- Semiconductors > Processors > Automotive Processors > DRAx Infotainment SoCs