Datasheet Texas Instruments DP83867CRRGZT — Datenblatt

Hersteller	Texas Instruments
Serie	DP83867CR
Artikelnummer	DP83867CRRGZT

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Design Kits und Evaluierungsmodule

• Evaluation Modules & Boards: DP83867ERGZ-R-EVM
  DP83867ERGZ RGMII 1000M/100M/10M Ethernet PHY Evaluation Module
  Lifecycle Status: Active (Recommended for new designs)
  
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Anwendungshinweise

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  Importance of Latency in Factory Automation
  PDF, 196 Kb, Datei veröffentlicht: Oct 25, 2015
  Latency is a critical parameter in Ethernet networks developed for Factory Automation applications. Latency is not a defined value for Ethernet as specified by the IEEE 802.3 standard. Nor is Ethernet inherently synchronous or repeatable. This disconnect between the inherent characteristics of Ethernet and the needs of Factory Automation applications must be bridged though care
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  RGMII Interface Timing Budgets
  PDF, 185 Kb, Datei veröffentlicht: Oct 28, 2015
  RGMII Interface Timing Budgets is intended to serve as a guideline for developing a timing budget when using the RGMII v1.3 and v2.0 standard with a Gigabit PHY transceiver like the DP83867.
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  DP83867 Troubleshooting Guide (Rev. A)
  PDF, 700 Kb, Revision: A, Datei veröffentlicht: Apr 6, 2016
  A 10/100/1000 Ethernet Physical Layer device has multiple connections and many possible configurationoptions. While the DP83867 is designed with a priority on ease of use, there are many factors to considerduring initial board bring up. This application note provides guidance on the key criteria to verify in order toexpedite initial validation of DP83867 applications.
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  DP83867E/IS/CS/IR/CR RGZ Power Consumption Data
  PDF, 92 Kb, Datei veröffentlicht: Oct 7, 2015
  Power consumption on an Ethernet PHY is affected by different operating conditions. System design around Ethernet products requires accurate power consumption numbers for component selection, thermal management and power distribution planning. This application report details power consumption of DP83867 in different conditions.
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  How to Configure DP83867 Start of Frame
  PDF, 78 Kb, Datei veröffentlicht: Oct 27, 2015
  The DP83867 can detect a Start of Frame Delimiter (SFD) for transmit and receive packets and output a pulse via a GPIO that can be used to assess the latency of the link between the DP83867 and a timestamp capable partner. For real-time systems and systems implementing the IEEE 1588 Precision Time Protocol (PTP) to timestamp packets for synchronizing devices across the network,
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  How to Configure DP838XX for Ethernet Compliance and Loopback Testing (Rev. A)
  PDF, 820 Kb, Revision: A, Datei veröffentlicht: Jan 31, 2017
  This application report covers how to setup and configure the DP838xx PHY (using the customer EVM) forEthernet Physical Layer Compliance (IEEE 802.3) testing as the device under test (DUT). This applicationnote primarily uses DP83867 as an example, but any DP838xx can use these procedures for compliancetesting.Refer to DP83822 IEEE 802.3u Compliance and Debug (SNLA266) for a DP83822 specif

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Herstellerklassifikation

• Semiconductors > Interface > Ethernet > Ethernet PHY