Datasheet Texas Instruments CDCLVP110 — Datenblatt
Hersteller | Texas Instruments |
Serie | CDCLVP110 |
1:10 LVPECL / HSTL zu LVPECL Clock Driver
Datenblätter
Low-Voltage 1:10 LVPECL/HSTL With Selectable Input Clock Driver datasheet
PDF, 653 Kb, Revision: D, Datei veröffentlicht: Jan 11, 2011
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Preise
Status
CDCLVP110MVFR | CDCLVP110MVFRG4 | CDCLVP110VF | CDCLVP110VFG4 | CDCLVP110VFR | CDCLVP110VFRG4 | |
---|---|---|---|---|---|---|
Lifecycle Status | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) |
Manufacture's Sample Availability | No | No | Yes | No | No | Yes |
Verpackung
CDCLVP110MVFR | CDCLVP110MVFRG4 | CDCLVP110VF | CDCLVP110VFG4 | CDCLVP110VFR | CDCLVP110VFRG4 | |
---|---|---|---|---|---|---|
N | 1 | 2 | 3 | 4 | 5 | 6 |
Pin | 32 | 32 | 32 | 32 | 32 | 32 |
Package Type | VF | VF | VF | VF | VF | VF |
Industry STD Term | LQFP | LQFP | LQFP | LQFP | LQFP | LQFP |
JEDEC Code | S-PQFP-G | S-PQFP-G | S-PQFP-G | S-PQFP-G | S-PQFP-G | S-PQFP-G |
Package QTY | 1000 | 1000 | 250 | 250 | 1000 | 1000 |
Carrier | LARGE T&R | LARGE T&R | JEDEC TRAY (10+1) | JEDEC TRAY (10+1) | LARGE T&R | LARGE T&R |
Device Marking | CDCLVP110 | CDCLVP110 | CDCLVP110 | CDCLVP110 | CDCLVP110 | CDCLVP110 |
Width (mm) | 7 | 7 | 7 | 7 | 7 | 7 |
Length (mm) | 7 | 7 | 7 | 7 | 7 | 7 |
Thickness (mm) | 1.4 | 1.4 | 1.4 | 1.4 | 1.4 | 1.4 |
Pitch (mm) | .8 | .8 | .8 | .8 | .8 | .8 |
Max Height (mm) | 1.6 | 1.6 | 1.6 | 1.6 | 1.6 | 1.6 |
Mechanical Data | Herunterladen | Herunterladen | Herunterladen | Herunterladen | Herunterladen | Herunterladen |
Parameter
Parameters / Models | CDCLVP110MVFR | CDCLVP110MVFRG4 | CDCLVP110VF | CDCLVP110VFG4 | CDCLVP110VFR | CDCLVP110VFRG4 |
---|---|---|---|---|---|---|
Additive RMS Jitter(Typ), fs | 300 | 300 | 300 | 300 | 300 | 300 |
Input Frequency(Max), MHz | 3500 | 3500 | 3500 | 3500 | 3500 | 3500 |
Input Level | HSTL,LVPECL | HSTL,LVPECL | HSTL,LVPECL | HSTL,LVPECL | HSTL,LVPECL | HSTL,LVPECL |
Number of Outputs | 10 | 10 | 10 | 10 | 10 | 10 |
Operating Temperature Range, C | -40 to 85 | -40 to 85 | -40 to 85 | -40 to 85 | -40 to 85 | -40 to 85 |
Output Frequency(Max), MHz | 3500 | 3500 | 3500 | 3500 | 3500 | 3500 |
Output Level | LVPECL | LVPECL | LVPECL | LVPECL | LVPECL | LVPECL |
Package Group | LQFP | LQFP | LQFP | LQFP | LQFP | LQFP |
Package Size: mm2:W x L, PKG | 32LQFP: 81 mm2: 9 x 9(LQFP) | 32LQFP: 81 mm2: 9 x 9(LQFP) | 32LQFP: 81 mm2: 9 x 9(LQFP) | 32LQFP: 81 mm2: 9 x 9(LQFP) | 32LQFP: 81 mm2: 9 x 9(LQFP) | 32LQFP: 81 mm2: 9 x 9(LQFP) |
Rating | Catalog | Catalog | Catalog | Catalog | Catalog | Catalog |
VCC, V | 2.5,3.3 | 2.5,3.3 | 2.5,3.3 | 2.5,3.3 | 2.5,3.3 | 2.5,3.3 |
VCC Out, V | 2.5,3.3 | 2.5,3.3 | 2.5,3.3 | 2.5,3.3 | 2.5,3.3 | 2.5,3.3 |
Öko-Plan
CDCLVP110MVFR | CDCLVP110MVFRG4 | CDCLVP110VF | CDCLVP110VFG4 | CDCLVP110VFR | CDCLVP110VFRG4 | |
---|---|---|---|---|---|---|
RoHS | Compliant | Compliant | Compliant | Compliant | Compliant | Compliant |
Anwendungshinweise
- Advantage of Using TI's Lowest Jitter Differential Clock BufferPDF, 221 Kb, Datei veröffentlicht: Aug 20, 2003
Advantage of Using TI's Lowest Jitter Differential Clock Buffer at SONET Speed 622.08 MHz - PCB Layout Guidelines for CDCLVP110PDF, 70 Kb, Datei veröffentlicht: Jun 12, 2002
This application note describes various electrical and thermal performance considerations for TI's CDCLVP110. In addition, it provides recommendations for PCB layout as well as optimizing power consumption in a real system application. Finally, it shows examples of how to estimate the worst case chip temperature. - Clocking Design Guidelines: Unused PinsPDF, 158 Kb, Datei veröffentlicht: Nov 19, 2015
- DC-Coupling Between Differential LVPECL, LVDS, HSTL, and CMLPDF, 135 Kb, Datei veröffentlicht: Feb 19, 2003
- AC Coupling Between Differential LVPECL, LVDS, HSTL and CML (Rev. C)PDF, 417 Kb, Revision: C, Datei veröffentlicht: Oct 17, 2007
This report provides a quick reference of ac-coupling techniques for interfacing between different logic levels. The four differential signaling levels found in this reportare low-voltage positive-referenced emitter coupled logic (LVPECL), low-voltage differential signals (LVDS), high-speed transceiver logic (HSTL), and current-modelogic (CML). From these four differential signaling levels, 16
Modellreihe
Serie: CDCLVP110 (6)
Herstellerklassifikation
- Semiconductors> Clock and Timing> Clock Buffers> Differential