Datasheet Texas Instruments CDCLVP110VFG4 — Datenblatt

HerstellerTexas Instruments
SerieCDCLVP110
ArtikelnummerCDCLVP110VFG4
Datasheet Texas Instruments CDCLVP110VFG4

1:10 LVPECL / HSTL-LVPECL-Takttreiber 32-LQFP -40 bis 85

Datenblätter

Low-Voltage 1:10 LVPECL/HSTL With Selectable Input Clock Driver datasheet
PDF, 653 Kb, Revision: D, Datei veröffentlicht: Jan 11, 2011
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Preise

Status

Lifecycle StatusActive (Recommended for new designs)
Manufacture's Sample AvailabilityYes

Verpackung

Pin32
Package TypeVF
Industry STD TermLQFP
JEDEC CodeS-PQFP-G
Package QTY250
CarrierJEDEC TRAY (10+1)
Device MarkingCDCLVP110
Width (mm)7
Length (mm)7
Thickness (mm)1.4
Pitch (mm).8
Max Height (mm)1.6
Mechanical DataHerunterladen

Parameter

Additive RMS Jitter(Typ)300 fs
Input Frequency(Max)3500 MHz
Input LevelHSTL,LVPECL
Number of Outputs10
Operating Temperature Range-40 to 85 C
Output Frequency(Max)3500 MHz
Output LevelLVPECL
Package GroupLQFP
Package Size: mm2:W x L32LQFP: 81 mm2: 9 x 9(LQFP) PKG
RatingCatalog
VCC2.5,3.3 V
VCC Out2.5,3.3 V

Öko-Plan

RoHSCompliant

Anwendungshinweise

  • Advantage of Using TI's Lowest Jitter Differential Clock Buffer
    PDF, 221 Kb, Datei veröffentlicht: Aug 20, 2003
    Advantage of Using TI's Lowest Jitter Differential Clock Buffer at SONET Speed 622.08 MHz
  • PCB Layout Guidelines for CDCLVP110
    PDF, 70 Kb, Datei veröffentlicht: Jun 12, 2002
    This application note describes various electrical and thermal performance considerations for TI's CDCLVP110. In addition, it provides recommendations for PCB layout as well as optimizing power consumption in a real system application. Finally, it shows examples of how to estimate the worst case chip temperature.
  • Clocking Design Guidelines: Unused Pins
    PDF, 158 Kb, Datei veröffentlicht: Nov 19, 2015
  • DC-Coupling Between Differential LVPECL, LVDS, HSTL, and CML
    PDF, 135 Kb, Datei veröffentlicht: Feb 19, 2003
  • AC Coupling Between Differential LVPECL, LVDS, HSTL and CML (Rev. C)
    PDF, 417 Kb, Revision: C, Datei veröffentlicht: Oct 17, 2007
    This report provides a quick reference of ac-coupling techniques for interfacing between different logic levels. The four differential signaling levels found in this reportare low-voltage positive-referenced emitter coupled logic (LVPECL), low-voltage differential signals (LVDS), high-speed transceiver logic (HSTL), and current-modelogic (CML). From these four differential signaling levels, 16

Modellreihe

Herstellerklassifikation

  • Semiconductors > Clock and Timing > Clock Buffers > Differential