Datasheet Texas Instruments CDCLVD110 — Datenblatt

HerstellerTexas Instruments
SerieCDCLVD110
Datasheet Texas Instruments CDCLVD110

1 bis 10 LVDS-Taktpuffer bis 900 MHz mit minimalem Versatz für die Taktverteilung

Datenblätter

Programmable Low-Voltage 1:10 LVDS Clock Driver datasheet
PDF, 513 Kb, Revision: C, Datei veröffentlicht: Jan 14, 2008
Auszug aus dem Dokument

Preise

Status

CDCLVD110VFCDCLVD110VFG4CDCLVD110VFRCDCLVD110VFRG4
Lifecycle StatusNRND (Not recommended for new designs)NRND (Not recommended for new designs)NRND (Not recommended for new designs)NRND (Not recommended for new designs)
Manufacture's Sample AvailabilityNoNoNoNo

Verpackung

CDCLVD110VFCDCLVD110VFG4CDCLVD110VFRCDCLVD110VFRG4
N1234
Pin32323232
Package TypeVFVFVFVF
Industry STD TermLQFPLQFPLQFPLQFP
JEDEC CodeS-PQFP-GS-PQFP-GS-PQFP-GS-PQFP-G
Package QTY25025010001000
CarrierJEDEC TRAY (10+1)JEDEC TRAY (10+1)LARGE T&RLARGE T&R
Device MarkingCDCLVD110CDCLVD110CDCLVD110CDCLVD110
Width (mm)7777
Length (mm)7777
Thickness (mm)1.41.41.41.4
Pitch (mm).8.8.8.8
Max Height (mm)1.61.61.61.6
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Öko-Plan

CDCLVD110VFCDCLVD110VFG4CDCLVD110VFRCDCLVD110VFRG4
RoHSCompliantCompliantCompliantCompliant

Anwendungshinweise

  • Benefits of Using TI's Non-PLL Clock Buffer: Best in Class Phase Noise/Phase
    PDF, 560 Kb, Datei veröffentlicht: Jul 18, 2003
    This application report presents various jitter and phase noise measurements of three differential clock drivers. A Texas Instruments device was compared to two independent competitor devices. This report proves that clock buffer selection does have an impact on the total system timing budget, particularly when the system has two different input signals connected. Buffers must be able to resist th
  • DC-Coupling Between Differential LVPECL, LVDS, HSTL, and CML
    PDF, 135 Kb, Datei veröffentlicht: Feb 19, 2003
  • AC Coupling Between Differential LVPECL, LVDS, HSTL and CML (Rev. C)
    PDF, 417 Kb, Revision: C, Datei veröffentlicht: Oct 17, 2007
    This report provides a quick reference of ac-coupling techniques for interfacing between different logic levels. The four differential signaling levels found in this reportare low-voltage positive-referenced emitter coupled logic (LVPECL), low-voltage differential signals (LVDS), high-speed transceiver logic (HSTL), and current-modelogic (CML). From these four differential signaling levels, 16

Modellreihe

Herstellerklassifikation

  • Semiconductors> Clock and Timing> Clock Buffers> Differential