Datasheet Texas Instruments CDCEL949 — Datenblatt
| Hersteller | Texas Instruments |
| Serie | CDCEL949 |
Programmierbarer 4-PLL-VCXO-Taktsynthesizer mit 1,8-V-LVCMOS-Ausgängen
Datenblätter
CDCE(L)913: Flexible Low Power LVCMOS Clock Generator With SSC Support for EMI Reduction datasheet
PDF, 1.5 Mb, Revision: F, Datei veröffentlicht: Oct 27, 2016
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Status
| CDCEL949PW | CDCEL949PWG4 | CDCEL949PWR | CDCEL949PWRG4 | |
|---|---|---|---|---|
| Lifecycle Status | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) |
| Manufacture's Sample Availability | Yes | Yes | Yes | Yes |
Verpackung
| CDCEL949PW | CDCEL949PWG4 | CDCEL949PWR | CDCEL949PWRG4 | |
|---|---|---|---|---|
| N | 1 | 2 | 3 | 4 |
| Pin | 24 | 24 | 24 | 24 |
| Package Type | PW | PW | PW | PW |
| Industry STD Term | TSSOP | TSSOP | TSSOP | TSSOP |
| JEDEC Code | R-PDSO-G | R-PDSO-G | R-PDSO-G | R-PDSO-G |
| Package QTY | 60 | 60 | 2000 | 2000 |
| Carrier | TUBE | TUBE | LARGE T&R | LARGE T&R |
| Device Marking | CDCEL949 | CDCEL949 | CDCEL949 | CDCEL949 |
| Width (mm) | 4.4 | 4.4 | 4.4 | 4.4 |
| Length (mm) | 7.8 | 7.8 | 7.8 | 7.8 |
| Thickness (mm) | 1 | 1 | 1 | 1 |
| Pitch (mm) | .65 | .65 | .65 | .65 |
| Max Height (mm) | 1.2 | 1.2 | 1.2 | 1.2 |
| Mechanical Data | Herunterladen | Herunterladen | Herunterladen | Herunterladen |
Parameter
| Parameters / Models | CDCEL949PW | CDCEL949PWG4 | CDCEL949PWR | CDCEL949PWRG4 |
|---|---|---|---|---|
| Divider Ratio | Universal | Universal | Universal | Universal |
| Function | Clock Synthesizer | Clock Synthesizer | Clock Synthesizer | Clock Synthesizer |
| Input Level | Crystal, LVCMOS | Crystal, LVCMOS | Crystal, LVCMOS | Crystal, LVCMOS |
| Jitter-Peak to Peak(P-P) or Cycle to Cycle, C-C | 60 ps | 60 ps | 60 ps | 60 ps |
| Number of Outputs | 9 | 9 | 9 | 9 |
| Operating Temperature Range, C | -40 to 85 | -40 to 85 | -40 to 85 | -40 to 85 |
| Output Frequency(Max), MHz | 230 | 230 | 230 | 230 |
| Output Level | LVCMOS | LVCMOS | LVCMOS | LVCMOS |
| Output Skew, ps | 150 | 150 | 150 | 150 |
| Package Group | TSSOP | TSSOP | TSSOP | TSSOP |
| Package Size: mm2:W x L, PKG | 24TSSOP: 50 mm2: 6.4 x 7.8(TSSOP) | 24TSSOP: 50 mm2: 6.4 x 7.8(TSSOP) | 24TSSOP: 50 mm2: 6.4 x 7.8(TSSOP) | 24TSSOP: 50 mm2: 6.4 x 7.8(TSSOP) |
| Programmability | EEPROM | EEPROM | EEPROM | EEPROM |
| Rating | Catalog | Catalog | Catalog | Catalog |
| Special Features | Integrated EEPROM,Multiplier/Divider,Spread Spectrum Clocking (SSC) | Integrated EEPROM,Multiplier/Divider,Spread Spectrum Clocking (SSC) | Integrated EEPROM,Multiplier/Divider,Spread Spectrum Clocking (SSC) | Integrated EEPROM,Multiplier/Divider,Spread Spectrum Clocking (SSC) |
| VCC, V | 1.8 | 1.8 | 1.8 | 1.8 |
| VCC Core, V | 1.8 | 1.8 | 1.8 | 1.8 |
| VCC Out, V | 1.8 | 1.8 | 1.8 | 1.8 |
Öko-Plan
| CDCEL949PW | CDCEL949PWG4 | CDCEL949PWR | CDCEL949PWRG4 | |
|---|---|---|---|---|
| RoHS | Compliant | Compliant | Compliant | Compliant |
Anwendungshinweise
- VCXO Application Guideline for CDCE(L)9xx Family (Rev. A)PDF, 107 Kb, Revision: A, Datei veröffentlicht: Apr 23, 2012
- Practical consideration on choosing a crystal for CDCE(L)9xx familyPDF, 60 Kb, Datei veröffentlicht: Mar 24, 2008
- Usage of I2C for CDCE(L)949, CDCE(L)937, CDCE(L)925, CDCE(L)913PDF, 297 Kb, Datei veröffentlicht: Sep 23, 2009
This document presents a method to smoothly change frequency by IВІCв„ў protocol on Texas Instruments CDCE(L)949, CDCE(L)937, CDCE(L)925, CDCE(L)913 Clock Synthesizers, thus avoiding unnecessary intermediate frequencies. It also includes a code example to generate the IВІC protocol for the CDCE(L)9xx with the TMS320C645x. - Generating Low Phase-Noise Clocks for Audio Data Converters from Low FrequencyPDF, 860 Kb, Datei veröffentlicht: Mar 31, 2008
Generating a high-frequency system clock Fs (128fs to 768fs) from a low-frequency sampling clock fs (10 kHz to 200 kHz) is challenging, while attempting to maintain low phase jitter. A traditional phase-lock loop (PLL) can do the frequency translation, but the added phase jitter prevents the generated system clock signal from effectively driving high-performance audio data converters. This applica - Troubleshooting I2C Bus ProtocolPDF, 184 Kb, Datei veröffentlicht: Oct 19, 2009
When using the I2Cв„ў bus protocol, the designer must ensure that the hardware complies with the I2C standard. This application report describes the I2C protocol and provides guidelines on debugging a missing acknowledgment, selecting the pullup resistors, or meeting the maximum capacitance load of an I2C bus. A conflict occurs if devices sharing the I2C bus have the same slave address. This
Modellreihe
Serie: CDCEL949 (4)
Herstellerklassifikation
- Semiconductors> Clock and Timing> Clock Generators> Spread-Spectrum Clocks