Datasheet Texas Instruments CDCEL913IPWRQ1 — Datenblatt

HerstellerTexas Instruments
SerieCDCEL913-Q1
ArtikelnummerCDCEL913IPWRQ1
Datasheet Texas Instruments CDCEL913IPWRQ1

Programmierbarer 1-PLL-VCXO-Taktsynthesizer für den Automobilkatalog mit 1,8-V-LVCMOS-Ausgängen 14-TSSOP -40 bis 85

Datenblätter

CDCEx913-Q1 Programmable 1-PLL VCXO Clock Synthesizer With 1.8-V, 2.5-V, and 3.3-V Outputs datasheet
PDF, 1.5 Mb, Revision: C, Datei veröffentlicht: Nov 9, 2016
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Preise

Status

Lifecycle StatusActive (Recommended for new designs)
Manufacture's Sample AvailabilityYes

Verpackung

Pin14
Package TypePW
Industry STD TermTSSOP
JEDEC CodeR-PDSO-G
Package QTY2000
CarrierLARGE T&R
Device MarkingCEL913Q
Width (mm)4.4
Length (mm)5
Thickness (mm)1
Pitch (mm).65
Max Height (mm)1.2
Mechanical DataHerunterladen

Parameter

Divider RatioUniversal
Input LevelCrystal,LVCMOS
Jitter-Peak to Peak(P-P) or Cycle to Cycle60 ps C-C
Number of Outputs3
Operating Temperature Range-40 to 85 C
Output Frequency(Max)230 MHz
Output LevelLVCMOS
Output Skew150 ps
Package GroupTSSOP
Package Size: mm2:W x L14TSSOP: 32 mm2: 6.4 x 5(TSSOP) PKG
RatingAutomotive
Special FeaturesIntegrated EEPROM,Multiplier/Divider,Spread Spectrum Clocking (SSC)
VCC1.8,3.3 V

Öko-Plan

RoHSCompliant

Anwendungshinweise

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  • General I2C / EEPROM usage for the CDCE(L)9xx family
    PDF, 40 Kb, Datei veröffentlicht: Jan 26, 2010
  • VCXO Application Guideline for CDCE(L)9xx Family (Rev. A)
    PDF, 107 Kb, Revision: A, Datei veröffentlicht: Apr 23, 2012
  • Usage of I2C for CDCE(L)949, CDCE(L)937, CDCE(L)925, CDCE(L)913
    PDF, 297 Kb, Datei veröffentlicht: Sep 23, 2009
    This document presents a method to smoothly change frequency by IВІCв„ў protocol on Texas Instruments CDCE(L)949, CDCE(L)937, CDCE(L)925, CDCE(L)913 Clock Synthesizers, thus avoiding unnecessary intermediate frequencies. It also includes a code example to generate the IВІC protocol for the CDCE(L)9xx with the TMS320C645x.
  • Generating Low Phase-Noise Clocks for Audio Data Converters from Low Frequency
    PDF, 860 Kb, Datei veröffentlicht: Mar 31, 2008
    Generating a high-frequency system clock Fs (128fs to 768fs) from a low-frequency sampling clock fs (10 kHz to 200 kHz) is challenging, while attempting to maintain low phase jitter. A traditional phase-lock loop (PLL) can do the frequency translation, but the added phase jitter prevents the generated system clock signal from effectively driving high-performance audio data converters. This applica
  • Troubleshooting I2C Bus Protocol
    PDF, 184 Kb, Datei veröffentlicht: Oct 19, 2009
    When using the I2Cв„ў bus protocol, the designer must ensure that the hardware complies with the I2C standard. This application report describes the I2C protocol and provides guidelines on debugging a missing acknowledgment, selecting the pullup resistors, or meeting the maximum capacitance load of an I2C bus. A conflict occurs if devices sharing the I2C bus have the same slave address. This

Modellreihe

Serie: CDCEL913-Q1 (1)
  • CDCEL913IPWRQ1

Herstellerklassifikation

  • Semiconductors > Clock and Timing > Clock Generators > Spread-Spectrum Clocks