Datasheet Texas Instruments CDC516 — Datenblatt

Hersteller	Texas Instruments
Serie	CDC516

3,3-V-Phasenregelkreistakttreiber mit 3-Zustands-Ausgängen

Datenblätter

PDF, 479 Kb, Revision: B, Datei veröffentlicht: Dec 2, 2004

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	CDC516DGG	CDC516DGGG4	CDC516DGGR	CDC516DGGRG4
Lifecycle Status	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)
Manufacture's Sample Availability	No	Yes	Yes	No

	CDC516DGG	CDC516DGGG4	CDC516DGGR	CDC516DGGRG4
N	1	2	3	4
Pin	48	48	48	48
Package Type	DGG	DGG	DGG	DGG
Industry STD Term	TSSOP	TSSOP	TSSOP	TSSOP
JEDEC Code	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G
Package QTY	40	40	2000	2000
Carrier	TUBE	TUBE	LARGE T&R	LARGE T&R
Device Marking	CDC516	CDC516	CDC516	CDC516
Width (mm)	6.1	6.1	6.1	6.1
Length (mm)	12.5	12.5	12.5	12.5
Thickness (mm)	1.15	1.15	1.15	1.15
Pitch (mm)	.5	.5	.5	.5
Max Height (mm)	1.2	1.2	1.2	1.2
Mechanical Data	Herunterladen	Herunterladen	Herunterladen	Herunterladen

Parameters / Models	CDC516DGG	CDC516DGGG4	CDC516DGGR	CDC516DGGRG4
Absolute Jitter (Peak-to-Peak Cycle or Period Jitter), ps	200	200	200	200
Number of Outputs	16	16	16	16
Operating Frequency Range(Max), MHz	125	125	125	125
Operating Frequency Range(Min), MHz	25	25	25	25
Package Group	TSSOP	TSSOP	TSSOP	TSSOP
Package Size: mm2:W x L, PKG	48TSSOP: 101 mm2: 8.1 x 12.5(TSSOP)	48TSSOP: 101 mm2: 8.1 x 12.5(TSSOP)	48TSSOP: 101 mm2: 8.1 x 12.5(TSSOP)	48TSSOP: 101 mm2: 8.1 x 12.5(TSSOP)
Rating	Catalog	Catalog	Catalog	Catalog
VCC, V	3.3	3.3	3.3	3.3
t(phase error), ps	400	400	400	400
tsk(o), ps	200	200	200	200

	CDC516DGG	CDC516DGGG4	CDC516DGGR	CDC516DGGRG4
RoHS	Compliant	Compliant	Compliant	Compliant

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High Speed Clock Distribution Design Techniques for CDC 509/516/2509/2510/2516 (Rev. A)
PDF, 109 Kb, Revision: A, Datei veröffentlicht: Sep 23, 1998
The memory bandwidth of high performance microprocessors is increasing at a rapid rate and the future memory bandwidth requirements are expected to keep increasing. The bandwidth requirements of RAM will be satisfied in the near term by using Synchronous DRAM. The need to drive multiple DRAM chips at high speeds with low skew necessitates the use of clock distribution devices with Phase Locked Loo

Serie: CDC516 (4)