Datasheet Texas Instruments CDC509 — Datenblatt
| Hersteller | Texas Instruments |
| Serie | CDC509 |
3,3-V-Phasenregelkreis-Treiber
Datenblätter
CDC509: 3.3-V Phase-Lock Loop Clock Driver datasheet
PDF, 612 Kb, Revision: C, Datei veröffentlicht: Dec 2, 2004
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Preise
Status
| CDC509PWR | CDC509PWRG4 | |
|---|---|---|
| Lifecycle Status | Active (Recommended for new designs) | Active (Recommended for new designs) |
| Manufacture's Sample Availability | Yes | Yes |
Verpackung
| CDC509PWR | CDC509PWRG4 | |
|---|---|---|
| N | 1 | 2 |
| Pin | 24 | 24 |
| Package Type | PW | PW |
| Industry STD Term | TSSOP | TSSOP |
| JEDEC Code | R-PDSO-G | R-PDSO-G |
| Package QTY | 2000 | 2000 |
| Carrier | LARGE T&R | LARGE T&R |
| Device Marking | CK509 | CK509 |
| Width (mm) | 4.4 | 4.4 |
| Length (mm) | 7.8 | 7.8 |
| Thickness (mm) | 1 | 1 |
| Pitch (mm) | .65 | .65 |
| Max Height (mm) | 1.2 | 1.2 |
| Mechanical Data | Herunterladen | Herunterladen |
Parameter
| Parameters / Models | CDC509PWR | CDC509PWRG4 |
|---|---|---|
| Absolute Jitter (Peak-to-Peak Cycle or Period Jitter), ps | 200 | 200 |
| Number of Outputs | 9 | 9 |
| Operating Frequency Range(Max), MHz | 125 | 125 |
| Operating Frequency Range(Min), MHz | 25 | 25 |
| Operating Temperature Range, C | 0 to 70 | 0 to 70 |
| Package Group | TSSOP | TSSOP |
| Package Size: mm2:W x L, PKG | 24TSSOP: 50 mm2: 6.4 x 7.8(TSSOP) | 24TSSOP: 50 mm2: 6.4 x 7.8(TSSOP) |
| Rating | Catalog | Catalog |
| VCC, V | 3.3 | 3.3 |
| t(phase error), ps | 480 | 480 |
| tsk(o), ps | 200 | 200 |
Öko-Plan
| CDC509PWR | CDC509PWRG4 | |
|---|---|---|
| RoHS | Compliant | Compliant |
Anwendungshinweise
- High Speed Clock Distribution Design Techniques for CDC 509/516/2509/2510/2516 (Rev. A)PDF, 109 Kb, Revision: A, Datei veröffentlicht: Sep 23, 1998
The memory bandwidth of high performance microprocessors is increasing at a rapid rate and the future memory bandwidth requirements are expected to keep increasing. The bandwidth requirements of RAM will be satisfied in the near term by using Synchronous DRAM. The need to drive multiple DRAM chips at high speeds with low skew necessitates the use of clock distribution devices with Phase Locked Loo
Modellreihe
Serie: CDC509 (2)
Herstellerklassifikation
- Semiconductors> Clock and Timing> Clock Buffers> Zero Delay Buffers