Datasheet Texas Instruments CDC3S04 — Datenblatt

Hersteller	Texas Instruments
Serie	CDC3S04

Quad-Sinus-Taktpuffer mit LDO

Datenblätter

PDF, 1.5 Mb, Revision: C, Datei veröffentlicht: Jul 25, 2012

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	CDC3S04YFFR
Lifecycle Status	Active (Recommended for new designs)
Manufacture's Sample Availability	Yes

Parameters / Models	CDC3S04YFFR
Additive RMS Jitter(Typ), fs	300
Input Frequency(Max), MHz	52
Input Level	SINE
Number of Outputs	4
Operating Temperature Range, C	-40 to 85
Output Frequency(Max), MHz	52
Output Level	SINE
Package Group	DSBGA
Package Size: mm2:W x L, PKG	See datasheet (DSBGA)
Rating	Catalog
VCC Out, V	1.8

	CDC3S04YFFR
RoHS	Compliant

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Using the CDC3S04
PDF, 110 Kb, Datei veröffentlicht: Apr 18, 2010
When designing a single-ended clock tree, a system designer can choose between two commonly-used waveform types: rectangular or sinusoidal. This application note gives a short overview of both signal types and shows the advantages and disadvantages of each using the CDC3S04 quad sine-wave clock buffer with an integrated low-dropout regulator (LDO). Additionally, the clipped sinusoidal waveform is
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Power Supply Rejection to Noise in Sinusoidal Clock Buffers: CDC3S04 (Rev. A)
PDF, 12.8 Mb, Revision: A, Datei veröffentlicht: Jun 21, 2010
This application report is an overview on how power supply noise affects some key specifications of the CDC3S04 sine wave buffer. The ripple in the power supply induces additional harmonics in the frequency spectrum and spurs in the phase noise plot, thus degrading the overall jitter and EMI performance. Decoupling capacitors significantly minimize these effects. This document provides guidelines

Serie: CDC3S04 (1)