Datasheet Texas Instruments CDC3RL02YFPR — Datenblatt

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SCHS371D – NOVEMBER 2009 – REVISED APRIL 2017 CDC3RL02 Low Phase-Noise Two-Channel Clock Fan-Out Buffer
1 Features 3 Description The CDC3RL02 is a two-channel clock fan-out buffer
and is ideal for use in portable end-equipment, such
as mobile phones, that require clock buffering with
minimal additive phase noise and fan-out capabilities.
It buffers a single master clock, such as a
temperature compensated crystal oscillator (TCXO)
to multiple peripherals. The device has two clock
request inputs (CLK_REQ1 and CLK_REQ2), each of
which enable a single clock output. 1 Low Additive Noise:
– –149 dBc/Hz at 10-kHz Offset Phase Noise
– 0.37 ps (RMS) Output Jitter
Limited Output Slew Rate for EMI Reduction
(1-to 5-ns Rise/Fall Time for 10-pF to 50-pF
Loads)
Adaptive Output Stage Controls Reflection
Regulated 1.8-V Externally Available I/O Supply …